# US 11,305,985 B2 · MEMS device and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,305,985 B2 - Document ID: US11305985B2 - Status: Granted - Kind: B2 - Application number: 16/633,244 - Filed: 2019-03-25 - Published: 2020-12-17 - Granted: 2022-04-19 - Earliest claimed: 2018-12-29 - Assignees: Hangzhou Silan Integrated Circuit Co., Ltd; Hangzhou Silan Microelectronics Co., Ltd. - Applicants: Hangzhou Silan Integrated Circuit Co., Ltd.; Hangzhou Silan Microelectronics CO., LTD. - Inventors: Wei Sun; Yongxiang Wen; Chen Liu; Junshan Ge; Zhijian Ma - Web page: https://patentgrep.com/patent/US11305985B2 ## CPC - B81B 7/02: containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS] (B81B7/04 takes precedence) - H03H 3/02: for the manufacture of piezoelectric or electrostrictive resonators or networks (H03H3/08 takes precedence) - B81C 1/00246: {Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate} - H03H 3/0073: {Integration with other electronic structures} - H03H 9/0557: {the other elements being buried in the substrate} - H03H 9/173: {Air-gaps} - H10N 30/074: by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing - H10N 30/706: {characterised by the underlying bases, e.g. substrates} - H10N 30/802: {Circuitry or processes for operating piezoelectric or electrostrictive devices not otherwise provided for, e.g. drive circuits} - H10N 30/875: {Further connection or lead arrangements, e.g. flexible wiring boards, terminal pins} - H10N 30/877: {Conductive materials} - B81C 2203/0735: Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit - B81C 2203/0771: Stacking the electronic processing unit and the micromechanical structure - H03H 2003/021: {the resonators or networks being of the air-gap type} - B81B: MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES (piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/00, H10N35/00) - H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P) - B81C: PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS (making microcapsules or microballoons B01J13/02; processes or apparatus specially adapted for the manufacture or treatment of piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/01) - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR ## Abstract A MEMS device and a manufacturing method thereof. The manufacturing method comprises: forming a CMOS circuit; and forming a MEMS module on the CMOS circuit which is coupling to the MEMS module and configured to drive the MEMS module. Forming the MEMS module comprises: forming a protective layer; forming a sacrificial layer in the protective layer; forming a first electrode on the protective layer and on the sacrificial layer so that the first electrode covers the sacrificial layer, and electrically coupling the first electrode to the CMOS circuit; forming a piezoelectric layer on the first electrode and above the sacrificial layer; forming a second electrode on the piezoelectric layer and electrically coupling the second electrode to the CMOS circuit; forming a through hole to reach the sacrificial layer; and forming a cavity by removing the sacrificial layer through the through hole. ## Claims ### Claim 1 A manufacturing method of a MEMS device, comprising: forming a CMOS circuit; and forming a MEMS module on the CMOS circuit which is coupling to the MEMS module and configured to drive the MEMS module, wherein, the step of forming the MEMS module comprises: forming a protective layer; forming a first contact hole and the second contact hole in the protective layer; forming a sacrificial layer in the protective layer; forming a first electrode on the protective layer and on the sacrificial layer so that the first electrode covers the sacrificial layer, and electrically coupling the first electrode to the CMOS circuit; forming a piezoelectric layer on the first electrode and above the sacrificial layer; forming a second electrode on the piezoelectric layer and electrically coupling the second electrode to the CMOS circuit; forming a through hole in the first electrode or in the protective layer to reach the sacrificial layer; and forming a cavity by removing the sacrificial layer through the through hole, wherein, the step of forming the CMOS circuit comprises: forming a plurality of second interconnecting holes in a second dielectric layer, and patterning a second wiring layer on the second dielectric layer to form a plurality of second interconnecting leads each of which has one end in one of the plurality of second interconnecting holes and the other end extending into the first contact hole and the second contact hole, the first electrode is electrically coupling to the CMOS circuit through the first contact hole, and the second electrode is electrically coupling to the CMOS circuit through the second contact hole. ### Claim 2 (depends on 1) The manufacturing method according to claim 1, wherein the step of forming the sacrificial layer comprises: forming an opening in the protective layer; filling the opening with a sacrificial material; and removing a part of the sacrificial material that is outside the opening. ### Claim 3 (depends on 2) The manufacturing method according to claim 2, wherein the sacrificial material comprises phosphosilicate glass. ### Claim 4 (depends on 1) The manufacturing method according to claim 1, wherein, the step of forming the first electrode comprises: forming a first conductive layer on the protective layer and on the sacrificial layer; and patterning the first conductive layer to form the first electrode, wherein a part of the first electrode is located in the first contact hole. ### Claim 5 (depends on 4) The manufacturing method according to claim 4, wherein, the step of forming the second electrode comprises: forming a second conductive layer on the protective layer and on the piezoelectric layer; patterning the second conductive layer to form the second electrode, wherein a part of the second electrode is located in the second contact hole. ### Claim 6 (depends on 1) The manufacturing method according to claim 1, wherein the step of forming the cavity comprises: removing the sacrificial layer though the through hole by a hydrofluoric acid vapor phase fumigation process. ### Claim 7 (depends on 6) The manufacturing method according to claim 6, wherein, the piezoelectric layer covers a part of the first electrode and exposes the through hole. ### Claim 8 (depends on 5) The manufacturing method according to claim 5, wherein the step of forming the CMOS circuit comprises: forming a first transistor and a second transistor on a substrate; and sequentially forming a first dielectric layer, a first wiring layer, the second dielectric layer and the second wiring layer on the first transistor and the second transistor. ### Claim 9 (depends on 8) The manufacturing method according to claim 8, wherein, the step of forming the CMOS circuit further comprises: forming a plurality of first interconnecting holes in the first dielectric layer before the step of forming the first wiring layer, and the step of forming the CMOS circuit further comprises: patterning the first wiring layer to form a plurality of first interconnecting leads each of which contacts the first transistor or the second transistor through one of the plurality of first interconnecting holes after the step of forming the first wiring layer. ### Claim 10 (depends on 9) The manufacturing method according to claim 9, each of the plurality of second interconnecting leads has one end connecting to one of the plurality of first interconnecting leads through one of the plurality of second interconnecting holes. ### Claim 11 (depends on 9) The manufacturing method according to claim 9, wherein the first transistor and the second transistor are coupling by one of the plurality of first interconnecting leads. ### Claim 12 (depends on 1) The manufacturing method according to claim 1, wherein the protective layer has an etching ratio greater than that of silicon dioxide. ### Claim 13 (depends on 1) The manufacturing method according to claim 1, wherein a material of the protective layer comprises silicon nitride. ### Claim 14 (depends on 1) The manufacturing method according to claim 1, wherein the protective layer has a thickness of more than 2 μm. ### Claim 15 (depends on 1) The manufacturing method according to claim 1, wherein the cavity has a depth ranging from 1 to 1.5 μm. ### Claim 16 (depends on 1) The manufacturing method according to claim 1, wherein, a material of the first electrode and the second electrode comprises molybdenum, and a material of the piezoelectric layer comprises aluminum nitride. ### Claim 17 (depends on 1) The manufacturing method according to claim 1, wherein the first electrode has a thickness ranging from 0.5 to 0.8 μm, and the second electrode has a thickness less than or equal to 0.5 μm. ### Claim 18 (depends on 1) The manufacturing method according to claim 1, wherein the MEMS device comprises a film bulk acoustic wave filter. ### Claim 19 A MEMS device comprising: a CMOS circuit; a MEMS module being located on the CMOS circuit which is coupling to the MEMS module and configured to drive the MEMS module, wherein, the MEMS module comprises: a protective layer on the CMOS circuit, the protective layer has a first contact hole and the second contact hole; a cavity being located in the protective layer; a first electrode being located on the protective layer and the cavity, which is electrically coupling to the CMOS circuit and covers the cavity; a piezoelectric layer being located on the first electrode and above the cavity; a second electrode being located on the piezoelectric layer and being electrically coupling to the CMOS circuit; and a through hole being located in the protective layer or in the first electrode to reach the cavity, wherein the piezoelectric layer exposes the through hole, the CMOS circuit comprises: a plurality of second interconnecting holes in a second dielectric layer, and a plurality of second interconnecting leads which has one end in one of the plurality of second interconnecting holes and the other end extending into the first contact hole and the second contact hole, the first electrode is electrically coupling to the CMOS circuit through the first contact hole, and the second electrode is electrically coupling to the CMOS circuit through the second contact hole. ### Claim 20 (depends on 19) The MEMS device according to claim 19, a part of the first electrode is located in the first contact hole, a part of the second electrode is located in the second contact hole. ### Claim 21 (depends on 19) The MEMS device according to claim 19, wherein the CMOS circuit comprises: a substrate; a first transistor and a second transistor being located on the substrate; a first dielectric layer being located on the first transistor and on the second transistor; a plurality of first interconnecting leads being located on the first dielectric layer; the second dielectric layer being located on the plurality of first interconnecting leads; and the plurality of second interconnecting leads being located on the second dielectric layer. ### Claim 22 (depends on 21) The MEMS device according to claim 21, wherein, the first dielectric layer has a plurality of first interconnecting holes, and each of the first interconnecting leads contact the first transistor or the second transistor through one of the plurality of first interconnecting holes, each of the plurality of second interconnecting leads has one end connecting with one of the plurality of first interconnecting leads through one of the plurality of second interconnecting holes. ### Claim 23 (depends on 22) The MEMS device according to claim 22, wherein the first transistor and the second transistor are coupling by one of the plurality of first interconnecting leads. ### Claim 24 (depends on 19) The MEMS device according to claim 19, wherein the protective layer has an etching ratio greater than that of silicon dioxide. ### Claim 25 (depends on 19) The MEMS device according to claim 19, wherein a material of the protective layer comprises silicon nitride. ### Claim 26 (depends on 19) The MEMS device according to claim 19, wherein the protective layer has a thickness greater than 2 μm. ### Claim 27 (depends on 19) The MEMS device according to claim 19, wherein the cavity has a depth ranging from 1 to 1.5 μm. ### Claim 28 (depends on 19) The MEMS device according to claim 19, wherein, a material of the first electrode and the second electrode comprises molybdenum, and a material of the piezoelectric layer comprises aluminum nitride. ### Claim 29 (depends on 19) The MEMS device according to claim 19, wherein, the first electrode has a thickness of 0.5 μm, and the second electrode has a thickness less than 0.5 μm. ### Claim 30 (depends on 19) A MEMS device according to claim 19, wherein the MEMS device is a film bulk acoustic wave filter.