Ferroelectric or paraelectric based sequential circuit

An apparatus comprising:

• a first minority gate to receive a clock, an inverted data input, a delayed and inverted version of the clock, and two inputs tied to ground;
• a second minority gate to receive an inverted version of the clock, a delayed version of the clock, and an input tied to ground;
• and
• a third minority gate to receive an output of the first minority gate, an output of the second minority gate, and an input tied to ground, wherein an output of the third minority gate is coupled to at least two inputs of the second minority gate.

A system comprising:

• a processor circuitry to execute one or more instructions;
• a communication interface communicatively coupled to the processor circuitry;
• and
• a memory coupled to the processor circuitry, wherein the processor circuitry comprises a sequential circuitry which includes:
• a first 5-input gate comprising non-linear polar material;
• a second 5-input gate comprising the non-linear polar material;
• a clock node coupled to a first input of the first 5-input gate;
• a data node coupled to the first 5-input gate;
• and
• a 3-input gate comprising the non-linear polar material, wherein a first output of the first 5-input gate is coupled to a first input of the 3-input gate, wherein a second output of the second 5-input gate is coupled to a second input of the 3-input gate, wherein an output of the 3-input gate is coupled an input of the second 5-input gate, and wherein the second 5-input gate is not connected to the data node.