Multimodal digital multiplication circuits and methods
AssigneeGroq, Inc.
InventorChristopher Aaron Clark
Life of this patent
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Abstract
Embodiments of the present disclosure pertain to multimodal digital multiplier circuits and methods. In one embodiment, partial product outputs of digital multiplication circuits are selectively inverted based on a mode control signal. The mode control signal may be set based on a format of the operands input to the multiplier. Example embodiments of the disclosure may multiply combinations of signed and unsigned input operands using different modes.
Claims18
A multimodal multiplier circuit comprising:
- a multiplier circuit configured to generate a plurality of partial products of a first operand and a second operand;
- a plurality of inverter circuits configured to:
- generate a first version of a first plurality of a first portion of the partial products and a second version of a second plurality of the first portion of the partial products based on a plurality of different bits of a mode control signal, and
- invert a first subset of a plurality of constant bit values and not invert a second subset of the constant bit values based on the plurality of different bits of the mode control signal to generate a version of the constant bit values;
- and
- an adder circuit configured to add the first version of the first plurality, the second version of the second plurality and a second portion of the partial products to generate bits of a product of the first and second operands.
A method performed by a multimodal multiplier circuit, the method comprising:
- generating, by a multiplier circuit of the multimodal multiplier circuit, a plurality of partial products of a first operand and a second operand;
- generating, by a plurality of inverter circuits of the multimodal multiplier circuit, a first version of a first plurality of a first portion of the partial products and a second version of a second plurality of the first portion of the partial products based on a plurality of different bits of a mode control signal;
- inverting, by the plurality of inverter circuits, a first subset of a plurality of constant bit values without inverting a second subset of the constant bit values based on the plurality of different bits of the mode control signal to generate a version of the constant bit values;
- and
- adding, by an adder circuit of the multimodal multiplier circuit, the first version of the first plurality, the second version of the second plurality and a second portion of the partial products to generate bits of a product of the first and second operands.
A non-transitory machine-readable medium storing a hardware description language program, the hardware description language program comprising sets of instructions, which when executed producing a digital circuit comprising:
- a multiplier circuit configured to generate a plurality of partial products of a first operand and a second operand;
- a plurality of inverter circuits configured to:
- generate a first version of a first plurality of a first portion of the partial products and a second version of a second plurality of the first portion of the partial products based on a plurality of different bits of a mode control signal, and
- invert a first subset of a plurality of constant bit values and not invert a second subset of the constant bit values based on the plurality of different bits of the mode control signal to generate a version of the constant bit values;
- and
- an adder circuit configured to add the first version of the first plurality, the second version of the second plurality and a second portion of the partial products to generate bits of a product of the first and second operands.
Dependencies are inferred from the claim text.