Cross-clock-domain processing circuit
AssigneeHuawei Technologies Co., Ltd.
InventorsYujing Bai, Xuhui Liu
Life of this patent
Estimating the term…
Abstract
A cross-clock-domain processing circuit configured to implement data processing between asynchronous clock domains with a relatively low latency. The cross-clock-domain processing circuit includes a jitter filtering circuit and a synchronization circuit. The jitter filtering circuit is configured to: perform jitter filtering on a clock recovered from input data; adjust a jitter-filtered clock phase; and output a processed input data clock as an output data clock to the synchronization circuit. The synchronization circuit is configured to perform cross-clock-domain synchronization on the input data based on the input data clock and the output data clock.
Claims20
A cross-clock-domain processing circuit, comprising:
- a jitter filtering circuit configured to:
- receive an input data clock having an input phase;
- perform jitter filtering processing and phase adjustment processing on the input data clock to generate an output data clock having an output phase aligned with the input phase;
- and
- output the output data clock, and wherein the input data clock is recovered from the input data;
- and
- a synchronization circuit configured to:
- receive the output data clock from the jitter filtering circuit;
- and
- generate synchronization data by performing cross-clock-domain synchronization on the input data based on the input data clock and the output data clock,
- wherein the synchronization data is in a clock domain of the output data clock.
A retimer configured to relay N channels of input data on a transmission link, wherein the retimer comprises:
- a jitter filtering circuit configured to:
- receive an input data clock having an input phase;
- perform jitter filtering and phase adjustment on the input data clock to generate an output data clock having an output phase aligned with the input phase;
- and
- output the output data clock, wherein the input data clock is any one of N recovered data clocks recovered by a clock recovery circuit from the N channels of input data, and wherein N≥1;
- and
- N synchronization circuits configured to receive the output data clock from the jitter filtering circuit, wherein each of the N synchronization circuits is configured to generate one of N channels of synchronization data by performing cross-clock-domain synchronization on each of the N channels of input data based on the input data clock and the output data clock, and wherein the N channels of synchronization data are in a clock domain of the output data clock.
A communication device, comprising:
- a printed circuit board (PCB);
- and
- a cross-clock-domain processing circuit disposed on the PCB, wherein the cross-clock-domain processing circuit comprises:
- a jitter filtering circuit configured to:
- receive an input data clock having an input phase;
- perform jitter filtering processing and phase adjustment processing on the input data clock to generate an output data clock having an output phase aligned with the input phase;
- and
- output the output data clock, wherein the cross-clock-domain processing circuit is configured to perform cross-clock-domain processing on input data, and wherein the input data clock is recovered from the input data;
- a synchronization circuit configured to:
- receive the processed input data clock from the jitter filtering circuit;
- and
- perform cross-clock-domain synchronization on the input data based on the input data clock and the output data clock, to generate synchronization data, wherein the synchronization data is in a clock domain of the output data clock.
Dependencies are inferred from the claim text.