Surface MESFET
AssigneeEmberion Oy
InventorsSami Kallioinen, Helena Pohjonen
Life of this patent
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Abstract
A MESFET transistor on a horizontal substrate surface with at least one wiring layer on the substrate surface. The transistor comprises source, drain and gate electrodes which are at least partly covered by a semiconducting channel layer. The source, drain and gate electrodes optionally comprise interface contact materials for changing the junction type between each electrode and the channel. The interface between the source electrode and the channel is an ohmic junction, the interface between the drain electrode and the channel is an ohmic junction, and the interface between the gate electrode and the channel is a Schottky junction. The substrate is a CMOS substrate.
Claims10
A metal-semiconductor field-effect transistor (MESFET) arrangement comprising:
- a first MESFET on a horizontal surface of a substrate with at least one wiring layer on the horizontal surface, wherein a topmost wiring layer of the at least one wiring layer comprises a first source region with a first bottom source electrode, a first drain region with a first bottom drain electrode, and a first gate region with a first bottom gate electrode, wherein each of the first bottom source electrode, the first bottom drain electrode and the first bottom gate electrode comprises at least an electrically conducting first metal contact,
- a first semiconducting channel layer on the topmost wiring layer, wherein the first semiconducting channel layer at least partly covers the first bottom source electrode, the first bottom drain electrode and the first bottom gate electrode,
- wherein an interface between the first bottom source electrode and the first semiconducting channel layer is an ohmic junction, an interface between the first bottom drain electrode and the first semiconducting channel layer is an ohmic junction, and an interface between the first bottom gate electrode and the first semiconducting channel layer is a Schottky junction,
- wherein the substrate is a complementary metal-oxide-semiconductor (CMOS) silicon substrate and the topmost wiring layer is connected to a CMOS circuit in the CMOS silicon substrate,
- wherein the topmost wiring layer lies between the substrate and the semiconducting channel layer in a vertical direction, and wherein the vertical direction is perpendicular to the horizontal surface of the substrate.
Dependencies are inferred from the claim text.