Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating
AssigneeZeno Semiconductor, Inc.
InventorYuniarto Widjaja
Life of this patent
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Abstract
Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.
Claims20
A semiconductor memory array comprising:
- a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell comprises:
- a capacitorless transistor having a floating body having a first conductivity type selected from n-type conductivity type and p-type conductivity type and configured to store data when power is applied to said memory cell and first and second regions located such that at least a portion of said floating body is located between said first and second regions;
- a nonvolatile memory comprising a resistance change element configured to store said data stored in said capacitorless transistor upon transfer thereto;
- a buried layer region having a second conductivity type selected from said n-type conductivity type and said p-type conductivity type and being different from said first conductivity type;
- wherein said buried layer region is commonly connected to at least two of said memory cells;
- wherein when said floating body has a first charge level, said nonvolatile memory is configured to a first resistivity level upon transfer of said data to said nonvolatile memory;
- and
- wherein when said floating body has a second charge level, said nonvolatile memory is configured to a second resistivity level upon transfer of said data to said nonvolatile memory.
An integrated circuit comprising:
- a semiconductor memory array comprising:
- a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell comprises:
- a capacitorless transistor having a floating body having a first conductivity type selected from n-type conductivity type and p-type conductivity type and configured to store data when power is applied to said memory cell and first and second regions located such that at least a portion of said floating body is located between said first and second regions;
- a nonvolatile memory comprising a resistance change element configured to store data stored in said capacitorless transistor upon transfer thereto;
- a buried layer region having a second conductivity type selected from said n-type conductivity type and said p-type conductivity type and being different from said first conductivity type;
- and
- a buried layer terminal electrically connected to said buried layer region;
- wherein when said floating body has a first charge level, said nonvolatile memory is configured to a first resistivity level upon transfer of said data to said nonvolatile memory;
- and
- wherein when said floating body has a second charge level, said nonvolatile memory is configured to a second resistivity level upon transfer of said data to said nonvolatile memory;
- and
- a control circuit configured to perform said transfer of said data.
Dependencies are inferred from the claim text.