Memory devices and memory operational methods

A memory writing method comprising:

• writing a plurality of memory cells which are coupled with a common conductor into one of a plurality of different memory states between first and second moments in time comprising:
• writing different ones of the memory cells which are coupled with the common conductor into the one memory state at different moments in time between the first and second moments in time;
• and
• maintaining the common conductor at a voltage potential which corresponds to the one memory state between the first and second moments in time;
• and
• wherein the writing the plurality of memory cells writes all of the memory cells which are coupled with the common conductor into the one memory state.

A memory system comprising:

• a common conductor;
• a plurality of memory cells that individually comprise a memory element;
• access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time, and wherein the memory elements have different electrical resistances corresponding to the different memory states of the memory cells;
• wherein the access circuitry is configured to maintain the common conductor at a first voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state;
• wherein the common conductor comprises first electrodes of the memory cells that contact the memory elements of the memory cells;
• wherein the access circuitry is configured to provide a second voltage potential corresponding to the one memory state to second electrodes of the memory cells at the different moments in time;
• and
• wherein the first and second voltage potentials are different.

A memory system comprising:

• a common conductor;
• a plurality of memory cells coupled with the common conductor;
• access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time;
• wherein the access circuitry is configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state;
• wherein the memory cells have memory elements which individually have different electrical resistances which correspond to the different memory states;
• and
• wherein the access circuitry is configured to assert different word lines which are coupled with the different ones of the memory cells at the different moments in time between the first and second moments in time.