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US 11,294,631 B2Granted
Full adder cell with improved power efficiency
AssigneeNVIDIA Corporation
InventorsIlyas Elkin, Ge Yang, Xi Zhang
Life of this patent
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Abstract
An adder circuit that includes an operand input and a second operand input to an XNOR cell. The XNOR cell is configured to provide the operand input and the second operand input to both a NAND gate and a first OAI cell. A second OAI cell transforms the output of the XNOR cell into a carry out signal.
Claims20
An adder circuit comprising:
- a first operand input and a second operand input to an XNOR cell;
- the XNOR cell configured to transform the first operand input and the second operand input utilizing a NAND gate and a first OAI cell;
- and
- a second OAI cell transforming an output of the XNOR cell into a carry out signal.
1 more element
A compressor circuit comprising:
- a full adder;
- a second full adder;
- and
- each full adder comprising:
- a first operand input and a second operand input to both of a NAND gate and a first OAI cell;
- and
- a second OAI cell transforming outputs of the NAND gate and the first OAI cell into a carry out signal.
4 more elements
An adder circuit comprising:
- an XNOR cell;
- a pass gate;
- an output stage at an output of the pass gate;
- and
- the XNOR cell configured to transform a first operand input and a second operand input into a propagate signal applied to each of the pass gate, the output stage, and an OAI cell.
2 more elements
Dependencies are inferred from the claim text.