Fault detection in hybrid DC-DC power convertors

A method for programming a fault detection circuit to detect a fault in a N-to-1 Dickson topology hybrid DC-DC power converter having an operating cycle and having at least (N−1) level-setting capacitors, an input terminal for receiving an input voltage, a ground terminal, and a switching node connected to an inductor;

• the method comprising configuring the fault detection circuit for:
• measuring a voltage at the switching node in first and second states in which first and second sets of level-setting capacitors are being charged and discharged, and discharged and charged, respectively;
• calculating a first error voltage, using a first calculation circuit, as a difference of the voltage at the switching node in the first state in an operating cycle and a next subsequent operating cycle;
• calculating a second error voltage, using a second calculation circuit, as a difference of the voltage at the switching node in the second state in an operating cycle and a next subsequent operating cycle;
• comparing the sum of the voltages, using a third calculation circuit, at the switching node in first and second states with 2/N times the input voltage, to determine a third error voltage;
• detecting a fault in response to either an absolute value of the third error voltage exceeding a first trip voltage level, or an absolute value of either the first or second error voltages exceeding a second trip voltage level.

An N-to-1 Dickson topology hybrid DC-DC power converter having at least (N−1) level-setting capacitors, an input terminal for receiving an input voltage, a ground terminal, and a switching node connected to an inductor, and operational according to an operating cycle comprising first, second and third states;

• and fault detection circuit comprising:
• a first measuring circuit configured to measure a first voltage, VSW1, at the switching node in the first state in which first and second sets of the level-setting capacitors are being charged and discharged;
• a first calculation circuit configured to calculate a first error voltage as a difference of the first voltage in one operating cycle (VSW1[n−1]) and in a next subsequent operating cycle (VSW1 [n]);
• a first fault circuit configured to provide a first fault output indicative of a fault in response to an absolute value of the first error voltage exceeding a short-circuit-trip level;
• a second measuring circuit configured to measure a second voltage, VSW2, at the switching node in the second state in which the first and second sets of the level-setting capacitors are being respectively discharged and charged;
• a second calculation circuit configured to calculate a second error voltage as a difference of the second voltage in one operating cycle (VSW2[n−1] and in a next subsequent operating cycle (VSW2[n]);
• and
• a second fault circuit configured to provide a second fault output indicative of a fault in response to an absolute value of the second error voltage exceeding the short-circuit-trip level.