US 11,290,118 B2Granted

Frequency synthesizer

AssigneeTexas Instruments Incorporated

InventorsSrinivas Theertham, Jagdish Chand, Yogesh Darwhekar, Subhashish Mukherjee, Jayawardan Janardhanan, Uday Kiran Meda, Arpan Sureshbhai Thakkar, Apoorva Bhatia, Pranav Kumar

Life of this patent

Estimating the term…

patentgrep

Loading patent…

Abstract

A frequency synthesizer includes a phase-locked loop (PLL). The PLL includes a first voltage-controlled oscillator (VCO) and a second VCO, each comprising an oscillator, a capacitor bank, and a bias circuit. The capacitor bank is configured to selectably adjust an output frequency of the oscillator. The bias circuit is configured to provide a bias current to the oscillator, and includes a current digital-to-analog converter (IDAC), and an amplifier coupled to the IDAC and configured to drive the oscillator.

Claims16

Dependent claims

A frequency synthesizer, comprising:

a phase-locked loop (PLL) comprising:
an oscillator control circuit comprising a capacitor control terminal and a current control terminal;
a voltage-controlled oscillator (VCO) circuit comprising:
an oscillator comprising a capacitor terminal and a bias current terminal;
a capacitor bank comprising
an oscillator terminal coupled to the capacitor terminal;
and
a selection terminal coupled to the capacitor control terminal;
a bias circuit comprising:
a current digital-to-analog converter (IDAC) comprising:
an input terminal coupled to the current control terminal;
and
an output terminal;
a filter capacitor terminal;
a bias current terminal;
and
an amplifier comprising:
an input terminal coupled to the output terminal of the IDAC;
and
an output terminal coupled to the filter capacitor terminal and the bias current terminal.

17 more elements

A frequency synthesizer, comprising:

a phase-locked loop (PLL), comprising:
a first voltage-controlled oscillator (VCO) and a second VCO, each comprising:
an oscillator;
a capacitor bank configured to selectably adjust an output frequency of the oscillator;
and
a bias circuit configured to provide a bias current to the oscillator, and comprising:
a current digital-to-analog converter (IDAC);
and
an amplifier coupled to the IDAC and configured to drive the oscillator;
wherein:
the PLL comprises:
a calibration look-up table;
and
a calibration circuit configured to:
initialize the calibration look-up table for a plurality of frequencies;
and
for each frequency of the plurality of frequencies:
determine which of the first VCO or the second VCO to use to generate the frequency;
and
store an identifier of the first VCO or the second VCO at a location of the calibration look-up table associated with the frequency.

17 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/128,791Filed 21 Dec 2020
Priority: IN 20204102450711 Jun 2020
Published: US 2021/0391866 A116 Dec 2021
Granted: 29 Mar 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H03L 7/087
Concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal: using at least two…
H03L 7/235
With pulse counters or frequency dividers: nested phase locked loops
H03L 7/085
Details of the phase-locked loop: concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its…
H03L 7/099
Details of the phase-locked loop: concerning mainly the controlled oscillator of the loop