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US 11,290,087 B2Granted
Positive logic digitally tunable capacitor
AssigneepSemi Corporation
InventorTero Tapio Ranta
Life of this patent
Estimating the term…
Abstract
Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.
Claims17
An integrated circuit block comprising:
- a first node;
- a second node;
- a resistive network;
- a series arrangement of two or more capacitors and a plurality of FET switches coupled between the first node and the second node;
- supply rails providing a first supply rail voltage and a second supply rail voltage, and
- a first control voltage and a second control voltage;
- wherein:
- a first capacitor of the two or more capacitors is coupled to the first node and a second capacitor of the two or more capacitors is coupled to the second node;
- the plurality of FET switches comprises a first end FET switch and a second end FET switch, the first end FET switch being closest to the first node and farthest from the second node and the second end FET switch being closest to the second node and farthest from the first node;
- each FET switch comprises a gate resistor coupling a FET switch gate to the first control voltage;
- the resistive network coupling the FET switch sources of the plurality of FET switches and/or FET switch drains of the plurality of FET switches to the second control voltage;
- the first control voltage and the second control voltage are non-negative voltages configured to enable and disable the FET switches and thereby adjusting a capacitance between the first node and the second node, and
- the second control voltage is a constant mid rail voltage regardless of ON or OFF states of the plurality of FET switches.
10 more elements
An integrated circuit comprising:
- a first node;
- a second node;
- a series arrangement of two or more capacitors and a plurality of FET switches;
- the plurality of FET switches comprising a first end FET switch and a second end FET switch, the first end FET switch being the closest to the first node and farthest from the second node and the second end FET switch being closest to the second node and farthest from the first node, and each of the plurality of FET switches comprising a gate resistor;
- a non-negative second supply voltage independent of a number of FET switches of the plurality of FET switches, the non-negative second supply voltage being a constant mid rail voltage;
- a resistive network, the resistive network coupling the drains and/or sources of the plurality of FET switches to the second supply voltage regardless of ON and OFF states of the plurality of FET switches, and
- a non-negative first supply voltage independent of a number of FET switches of the plurality of FET switches connecting the gate of each of the FET switches from the plurality of the FET switches to the first supply voltage via a corresponding gate resistor;
- wherein:
- the series arrangement of the two or more capacitors and the plurality of FET switches are coupled between the first and the second nodes;
- a first capacitor and a second capacitor of the two or more capacitors are coupled to the first node and the second node respectively, and
- the first and the second supply voltage are configured to enable or disable the FET switches to adjust a capacitance between the first node and the second node.
8 more elements
A method of digitally tuning a capacitor in an integrated circuit, the method comprising the steps of:
- providing a first node;
- providing a second node;
- providing a series arrangement of two or more capacitors and a plurality of FET switches;
- the plurality of FET switches comprising a first end FET switch and a second end FET switch, the first end FET switch being the closest to the first node and farthest from the second node and the second end FET switch being closest to the second node and farthest from the first node, and each of the plurality of FET switches comprising a gate resistor;
- providing a non-negative second supply voltage independent of a number of FET switches of the plurality of FET switches, the non-negative second supply voltage being a constant mid rail voltage;
- providing a resistive network, the resistive network coupling the drains and/or sources of the plurality of FET switches to the second supply voltage regardless of ON and OFF states of the plurality of FET switches;
- providing a non-negative first supply voltage independent of a number of FET switches of the plurality of FET switches connecting the gate of each of the FET switches from the plurality of the FET switches to the first supply voltage via a corresponding gate resistor;
- coupling the series arrangement of two or more capacitors and the plurality of FET switches between the first node and the second node;
- coupling a first capacitor of the two or more capacitors to the first node and coupling a second capacitor of the two or more capacitors to the second node;
- and
- enabling or disabling the FET switches using the first supply voltage and the second supply voltage and thereby adjusting a capacitance between the first node and the second node.
8 more elements
A digitally tunable capacitor circuit comprising a plurality of integrated circuit blocks configured in parallel, wherein an integrated circuit block of the plurality of integrated circuit blocks comprises:
- a first node;
- a second node;
- a resistive network;
- a series arrangement of two or more capacitors and a plurality of FET switches coupled between the first node and the second node;
- and
- supply rails providing a first supply voltage and a second supply voltage, the second supply voltage being a constant mid rail voltage;
- wherein:
- a first capacitor of the two or more capacitors is coupled to the first node and a second capacitor of the two or more capacitors is coupled to the second node;
- the plurality of FET switches comprises a first end FET switch and a second end FET switch, the first end FET switch being closest to the first node and farthest from the second node and the second end FET switch being closest to the second node and farthest from the first node;
- each FET switch comprises a gate resistor connecting a FET switch gate to the first supply voltage;
- the first supply voltage and the second supply voltage are non-negative supply voltages configured to enable and disable the FET switches and thereby adjusting a capacitance between the first node and the second node;
- and
- the resistive network comprises a plurality of resistors having first terminals connected to drains of corresponding FET switches and second terminals connected to the second supply voltage, the resistive network further comprising an end resistor connecting a source of the second end FET switch to the second supply voltage.
10 more elements
Dependencies are inferred from the claim text.