System and method for overlay error reduction
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHung-Chung Chien, Hao-Ken Hung, Chih-Chieh Yang, Ming-Feng Shieh, Chun-Ming Hu
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHung-Chung Chien, Hao-Ken Hung, Chih-Chieh Yang, Ming-Feng Shieh, Chun-Ming Hu
Estimating the term…
Semiconductor processing apparatuses and methods are provided in which a semiconductor wafer is flipped and then rotated between patterning of front and back sides of the semiconductor wafer by first and second reticles, respectively. In some embodiments, a method includes patterning, by a first reticle, a first layer on a first side of a semiconductor wafer while the first side of the semiconductor wafer is facing a first direction. The semiconductor wafer is then flipped. A second side of the semiconductor wafer that is opposite the first side faces the first direction after the flipping the semiconductor wafer. The semiconductor wafer is then rotated about a rotational axis extending along the first direction, and a second layer on the second side of the semiconductor wafer is patterned by a second reticle.
A method, comprising:
A semiconductor processing system, comprising:
A method, comprising:
Dependencies are inferred from the claim text.