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US 11,283,464 B2Granted
Compression and decompression engines and compressed domain processors
AssigneeSiliconIP, Inc.
InventorsDan E. Tamir, Dan Bruck
Life of this patent
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Abstract
Compressed domain processors configured to perform operations on data compressed in a format that preserves order. The Compressed domain processors may include operations such as addition, subtraction, multiplication, division, sorting, and searching. In some cases, compression engines for compressing the data into the desired formats are provided.
Claims20
A compressed domain processor comprising:
- a pre-arrangement-system comprising:
- a first priority encoder to encode odd bits associated with a first operand;
- a second priority encoder to encode odd bits associated with a second operand;
- a first right shift unit to arrange even bits associated with the first operand;
- a second right shift unit to arrange even bits associated with the second operand;
- an operation-execution-system comprising:
- a component to generate a result based at least in part on a first output of the first right shift unit and a second output of the second right shift unit;
- and
- a post-arrangement-system comprising:
- a left shift unit to insert a zero value between digits of a third operand based at least in part on the result output by the adder.
7 more elements
A compressed domain processor comprising:
- a pre-arrangement-system comprising:
- a subtraction component to subtract a first header of a first operand from a second header of a second operand and to output a sign and a value;
- a swap unit to determine an arrangement with respect to a first frustrum of the first operand and a second frustrum of a second operand based at least in part on the sign;
- an operation-execution-system comprising:
- a component to generate a result based at least in part on the first frustrum with the second frustrum;
- and
- a post-arrangement-system comprising:
- a right shift unit to generate a third frustrum based at least in part on the result output by the adder.
5 more elements
A compressed domain processor comprising:
- a pre-arrangement-system comprising:
- an adder component to add a first header of a first operand with a second header of a second operand and to output a value;
- an operation-execution-system comprising:
- a component to generate a result based at least in part on a first frustrum of the first operand and a second frustrum of the second operand;
- and
- a post-arrangement-system comprising:
- a left shift unit to generate a third frustrum based at least in part on the result output by the component.
4 more elements
Dependencies are inferred from the claim text.