Semiconductor logic element and a logic circuitry
AssigneeHyperion Semiconductors Oy
InventorArtto Aurola
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Abstract
Disclosed is a semiconductor logic element including a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. Also disclosed are different kinds of logic circuitries including the described logic element.
Claims22
A first semiconductor logic element comprising
- a field effect transistor of the first conductivity type hereinafter referred to as the first FET comprising a first source, a first drain, a first gate, and a first channel, and
- a field effect transistor of the second conductivity type hereinafter referred to as the second FET comprising a second source, a second drain, a second gate, and a second channel;
- wherein the first semiconductor logic element comprises a first internal node wherein the first internal node is at least partly formed with the first drain and the second gate,
- wherein the first gate is hereinafter referred to as a first input, the first input corresponding to the input of the first semiconductor logic element, wherein the first input is configured to be coupled either to a first input logic potential or to a second input logic potential,
- wherein the second drain is referred to as a first output, the first output corresponding to the output of the first semiconductor logic element,
- wherein the second source is a source of the first semiconductor logic element,
- wherein the first semiconductor logic element is configured so that when the first source is arranged at a first source potential and when the second source is at a first output logic potential and when the first input is at the first input logic potential, then the first channel is arranged to be in a conductive state adjusting the first internal node to the first source potential and thereby causing the second channel to be in a nonconductive state thus enabling the first output to be either at the first output logic potential or at a second output logic potential, and
- wherein the first semiconductor logic element is further configured so that when the first source is arranged at the first source potential and when the second source is at the first output logic potential and when the first input is at the second input logic potential, then the first channel is arranged to be in a nonconductive state enabling the first internal node to adjust to a potential causing the second channel to be in a conductive state thereby adjusting the first output to the first output logic potential, and
- wherein at least one plate capacitor is arranged between the first input and the first internal node.
Dependencies are inferred from the claim text.