US 11,283,434 B2 · Glitch protection system and reset scheme for secure memory devices

Abstract

A system and method for protecting against a voltage glitch are provided. Generally, the system includes a reset-detector coupled to a supply voltage (VCC) and to a power-on-reset (POR) block, and a glitch-detector coupled to VCC and the reset-detector. The reset-detector is operable to provide a signal to the POR block to generate a global-reset-signal when VCC decreases below a minimum and remains low for at least a first time. The glitch-detector is operable to provide a glitch-signal to the reset-detector to cause it to provide the signal to the POR block when VCC decreases below the minimum and remains low for at least a second time, where the second time is less than the first. The reset-detector can further include a retention-circuit operable to recall a glitch-signal was received and signal the POR block when VCC is restored. Other embodiments are also disclosed.

Claims20

Dependent claims

A glitch protection system comprising:

a first reset-detector coupled to a supply voltage (VCC) and to a power-on-reset (POR) block, the first reset-detector operable to provide a reset (VRST_DET) signal to the POR block to generate a global-reset-signal when the supply voltage decreases below a minimum supply voltage (VCCMIN) with at least a first slope magnitude (1st Tf) and remains low for at least a first time (1st tpD);
a glitch-detector coupled to the supply voltage and the first reset-detector, the glitch-detector operable to provide a glitch-detect (GLTH_DET) signal to the first reset-detector to cause the first reset-detector to provide the VRST_DET signal to the POR block when the supply voltage decreases below a glitch voltage (VCCGLITCH) with at least a second slope magnitude (2nd Tf) and remains low for at least a second time (2nd tpD);
and
wherein the second time is less than the first time, VCCGLITCH is less than VCCMIN for at least the second time (2nd tpD).

1 more element

Dependencies are inferred from the claim text.

Glitch protection system and reset scheme for secure memory devices

Life of this patent

Glitch protection system and reset scheme for secure memory devices

Life of this patent

Abstract

Claims20