High density vertical thyristor memory cell array with improved isolation
AssigneeKilopass Technology, Inc.
InventorsHarry Luan, Valery Axelrad
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Abstract
Isolation between vertical thyristor memory cells in an array is improved with isolation regions between the vertical thyristor memory cells. The isolation regions are formed by electrically isolating cores surrounded by insulating material, such as silicon dioxide, in trenches between the memory cells. The electrically isolating cores may be tubes of air or conducting rods. Methods of constructing the isolation regions in a processes for manufacturing vertical thyristor memory cell arrays are also disclosed.
Claims22
A method of manufacturing a memory cell array of vertical thyristor memory cells in a semiconductor substrate, the method comprising:
- etching a trench between vertical thyristor memory cells;
- depositing a portion of an insulating material non-conformally over the trench, the insulating material covering an electrically isolating core in the trench, the insulating material and electrically isolating core occupying an entirety of the trench;
- whereby the electrically isolating core and the insulating material in the trench isolates vertical thyristor memory cells on one side of the trench from vertical thyristor memory cells on the other side of the trench.
Dependencies are inferred from the claim text.