Reduced overhead gate level logic encryption

A circuit having a gate topology comprising:

• a logical gate with integrated key transistors having a logic structure that renders the circuit functional depending on inputs provided to the key transistors,
• wherein the key transistors comprise at least a PMOS stack and an NMOS stack, and wherein:
• the PMOS stack comprises a first PMOS switch having an input A and a second PMOS switch having an input B, wherein both the first and the second PMOS switches have sources to a voltage source and drains that serve as a source to a third PMOS switch, and wherein the third PMOS switch also receives an input KEY0 and has a drain that connects to an output OUT of the logical gate;
• the NMOS stack comprises a first NMOS switch having the input A and a second NMOS switch having the input B, wherein both the first and the second NMOS switches have sources to ground and drains that serve as a source to a third NMOS switch, and wherein the third NMOS switch also receives the input KEY0 and has a drain that connects to the output OUT of the logical gate;
• and
• input of a correct input KEY0 outputs a correct output OUT that renders the circuit functional, and input of an incorrect input KEY0 outputs an incorrect output OUT that renders the circuit not functional.