Receiver with enhanced clock and data recovery

An integrated circuit to receive an incoming data signal arriving at the integrated circuit via a conductive signal path, the incoming data signal carrying symbols, each symbol within a respective symbol period of the incoming data signal, the integrated circuit comprising:

• a clock and data recovery circuit, including
• first circuitry to measure the incoming data signal at respective data sampling times, each of the respective data sampling times corresponding to a respective one of the symbols, and to produce for each of the symbols a multi-bit value that represents magnitude of the incoming data signal measured at the respective data sampling time,
• second circuitry to measure voltage of the incoming data signal at expected symbol transition times, and to produce second values that each represent whether a recovered clock is early or late relative to the incoming data signal, and
• circuitry to advance or retard phase of the recovered clock dependent on changes in logic state between respective ones of the symbols;
• circuitry to evaluate a voltage margin characteristic dependent on the multibit values, and to identify and establish the respective data sampling times for the first circuitry so as to maximize the voltage margin characteristic, the respective data sampling times also being dependent on the recovered clock;
• and
• circuitry to compare the multibit values against at least one decision threshold, and to responsively produce a decision as to logic state of the corresponding ones of the symbols.

A method of operation of an integrated circuit that is to receive an incoming data signal arriving at the integrated circuit via a conductive signal path, the incoming data signal carrying symbols, each symbol within a respective symbol period of the incoming data signal, the method comprising, with circuitry:

• measuring the incoming data signal at respective data sampling times, each of the respective data sampling times corresponding to a respective one of the symbols, and producing for each of the symbols a multi-bit value that represents magnitude of the incoming data signal measured at the respective data sampling time;
• evaluating a voltage margin characteristic dependent the multibit values, and to identify and establish the respective data sampling times for the circuitry to measure so as to maximize the voltage margin characteristic;
• and
• comparing the multibit values against at least one decision threshold, and responsively producing a decision as to logic state of the corresponding ones of the symbols.