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US 11,276,711 B2Granted
Semiconductor device, display device, and electronic device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsHiroki Inoue, Fumika Akasawa
Life of this patent
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Abstract
A level shifter including a transistor that can be formed through the same process as a display portion is provided. A semiconductor device serves as a level shifter including transistors having the same conductivity type. The semiconductor device includes a so-called MIS capacitor in which metal, an insulator, and a semiconductor are stacked as a capacitor for boosting an input signal. Since the MIS capacitor is used, the gate-source voltage of a transistor for generating an output signal can be increased. Thus, boosting operation to generate the output signal can be performed more surely.
Claims13
A semiconductor device comprising:
- a level shifter over a substrate, the level shifter comprising:
- a first transistor, a second transistor, a third transistor, and a fourth transistor;
- and
- a first capacitor and a second capacitor,
- a controller IC over the substrate, the controller IC comprising a ninth transistor and a tenth transistor;
- and
- a gate driver over the substrate,
- wherein a chip of the controller IC is mounted on the substrate,
- wherein the level shifter and the gate driver are formed on the substrate,
- wherein the controller IC is operated at a first voltage,
- wherein the gate driver is operated at a second voltage which is higher than the first voltage and boosted by the level shifter,
- wherein a material of a channel formation region of the ninth transistor is different from a material of a channel formation region of the tenth transistor,
- wherein a gate of the first transistor and one of a source and a drain of the first transistor are electrically connected to a first wiring to which an input signal is supplied,
- wherein a gate of the second transistor, a gate of the fourth transistor, and a first electrode of the second capacitor are electrically connected to a second wiring to which an inverted input signal is supplied,
- wherein one of a source and a drain of the third transistor is electrically connected to a third wiring,
- wherein one of a source and a drain of the second transistor and one of a source and a drain of the fourth transistor are electrically connected to a fourth wiring that is different from the first wiring,
- wherein a first electrode of the first capacitor is electrically connected to the other of the source and the drain of the first transistor, the other of the source and the drain of the second transistor, and a gate of the third transistor,
- wherein a second electrode of the first capacitor is electrically connected to a second electrode of the second capacitor, the other of the source and the drain of the third transistor, and the other of the source and the drain of the fourth transistor,
- wherein the first capacitor and the second capacitor are a seventh transistor and an eighth transistor, respectively,
- wherein the first electrode of the first capacitor is a gate of the seventh transistor,
- wherein the second electrode of the first capacitor is a source and a drain of the seventh transistor,
- wherein the first electrode of the second capacitor is a gate of the eighth transistor,
- wherein the second electrode of the second capacitor is a source and a drain of the eighth transistor,
- wherein the semiconductor device is configured to generate an output signal by boosting the input signal, and
- wherein a capacitance of the second capacitor is larger than a capacitance of the first capacitor when voltages of the input signal and the inverted input signal change.
22 more elements
A semiconductor device comprising:
- a level shifter over a substrate, the level shifter comprising:
- a first transistor, a second transistor, a third transistor, and a fourth transistor;
- and
- a first capacitor and a second capacitor,
- a controller IC over the substrate, the controller IC comprising a ninth transistor and a tenth transistor;
- and
- a gate driver over the substrate,
- wherein a chip of the controller IC is mounted on the substrate,
- wherein the level shifter and the gate driver are formed on the substrate,
- wherein the controller IC is operated at a first voltage,
- wherein the gate driver is operated at a second voltage which is higher than the first voltage and boosted by the level shifter,
- wherein a material of a channel formation region of the ninth transistor is different from a material of a channel formation region of the tenth transistor,
- wherein a gate of the first transistor and one of a source and a drain of the first transistor are electrically connected to a first wiring to which an input signal is supplied,
- wherein a gate of the second transistor, a gate of the fourth transistor, and a first electrode of the second capacitor are electrically connected to a second wiring to which an inverted input signal is supplied,
- wherein one of a source and a drain of the third transistor is electrically connected to a third wiring,
- wherein one of a source and a drain of the second transistor and one of a source and a drain of the fourth transistor are electrically connected to a fourth wiring that is different from the first wiring,
- wherein a first electrode of the first capacitor is electrically connected to the other of the source and the drain of the first transistor, the other of the source and the drain of the second transistor, and a gate of the third transistor,
- wherein a second electrode of the first capacitor is electrically connected to a second electrode of the second capacitor, the other of the source and the drain of the third transistor, and the other of the source and the drain of the fourth transistor,
- wherein the first capacitor and the second capacitor are a seventh transistor and an eighth transistor, respectively,
- wherein the first electrode of the first capacitor is a gate of the seventh transistor,
- wherein the second electrode of the first capacitor is a source and a drain of the seventh transistor,
- wherein the first electrode of the second capacitor is a gate of the eighth transistor, and
- wherein the second electrode of the second capacitor is a source and a drain of the eighth transistor.
20 more elements
Dependencies are inferred from the claim text.