Memory component for deployment in a dynamic stripe width memory system
AssigneeRambus Inc.
InventorsFrederick A. Ware, John Eric Linstadt, Kenneth L. Wright
Life of this patent
Estimating the term…
Abstract
In a memory component having a page buffer with 2N independently accessible regions, N bits of a command/address value are decoded to access contents within a first one of the 2N page-buffer regions if a configuration value specifies a first addressing resolution and, if the configuration value specifies a second addressing resolution, a composite address that includes fewer than N bits of the command/address value together with a plurality of bits generated within the memory component to access contents within a second one of the 2N page-buffer regions.
Claims20
A method of operation within an integrated-circuit memory component, the method comprising:
- receiving a configuration value;
- receiving command/address value;
- if the configuration value specifies a first addressing resolution, decoding N bits of the command/address value to access contents within a first one of 2N independently accessible regions of a page buffer;
- and
- if the configuration value specifies a second addressing resolution:
- decoding a first composite address that includes fewer than N bits of the command/address value together with a plurality of bits generated by a counter circuit within the memory component to access contents within a second one of the 2N independently accessible regions of the page buffer, and
- decoding a second composite address that includes the fewer than N bits of the command/address value together with a plurality of bits having a fixed and predetermined state to access contents within a third one of the 2N independently accessible regions of the page buffer.
An integrated-circuit memory component:
- a programmable register to store a configuration value;
- a first page buffer having 2N independently accessible regions;
- a command/address interface to receive command/address value;
- and
- access control circuitry to:
- decode N bits of the command/address value to access contents within a first one of the 2N independently accessible regions of the first page buffer if the configuration value specifies a first addressing resolution;
- and
- if the configuration value specifies a second addressing resolution:
- decode a first composite address that includes fewer than N bits of the command/address value together with a plurality of bits generated within the memory component to access contents within a second one of the 2N independently accessible regions of the first page buffer, and
- decode a second composite address that includes the fewer than N bits of the command/address value together with a plurality of bits having a fixed and predetermined state to access contents within a third one of the 2N independently accessible regions of the page buffer.
An integrated-circuit memory component comprising:
- a page buffer having 2N independently accessible regions;
- means for storing a configuration value;
- means for receiving command/address value;
- and
- means for:
- decoding N bits of the command/address value to access contents within a first one of the 2N independently accessible regions of the page buffer if the configuration value specifies a first addressing resolution;
- and
- if the configuration value specifies a second addressing resolution:
- decoding a first composite address that includes fewer than N bits of the command/address value together with a plurality of bits generated within the memory component to access contents within a second one of the 2N independently accessible regions of the page buffer, and
- decoding a second composite address that includes the fewer than N bits of the command/address value together with a plurality of bits having a fixed and predetermined state to access contents within a third one of the 2N independently accessible regions of the page buffer.
Dependencies are inferred from the claim text.