Compact offset drift trim implementation

A circuit comprising:

• a first transistor having a control terminal, a first terminal, and a second terminal, the control terminal is coupled to a first differential input terminal, and the second terminal is coupled to a first terminal of an error correction circuit;
• a second transistor having a control terminal, a first terminal, and a second terminal, the control terminal is coupled to a second differential input terminal, the first terminal is coupled to the first terminal of the first transistor, and the second terminal is coupled to a second terminal of the error correction circuit;
• a third transistor having a control terminal, a first terminal, and a second terminal, the first terminal is coupled to the first terminal of the error correction circuit;
• a fourth transistor having a control terminal, a first terminal, and a second terminal, the control terminal is coupled to the control terminal of the third transistor, and the first terminal is coupled to the second terminal of the error correction circuit;
• and
• an output amplifier stage with an input coupled to the second terminal of the fourth transistor and an output coupled to an output terminal.

An error correction circuit comprising:

• a first transistor having a control terminal, a first terminal, and a second terminal, the second terminal is coupled to a current source through a first resistor, and the control terminal is coupled to a first differential voltage output and to the first terminal through a second resistor and a third resistor;
• a second transistor having a control terminal, a first terminal, and a second terminal, the second terminal is coupled to the current source through a fourth resistor, and the control terminal is coupled to a second differential voltage output through a fifth resistor and to the first terminal through the fifth resistor and a sixth resistor;
• a transconductance stage having a differential input coupled to the first differential voltage output and the second differential voltage output, and a differential output coupled to a first differential current output and a second differential current output;
• and
• a polarity selection switch coupled to the first differential current output and the second differential current output, and having a differential error correction current output.