Cache address mapping method and related device
AssigneeHuawei Technologies Co., Ltd.
InventorsYandong Lv, Jianjiang Ceng
Life of this patent
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Abstract
This application discloses a cache address mapping method and a related device. The method includes: obtaining a binary file, the binary file including a first hot section; obtaining alignment information of a second hot section, the second hot section is a hot section that has been loaded into a cache, and the alignment information includes a set index of a last cache set occupied by the second hot section; and performing an offset operation on the first hot section based on the alignment information. According to embodiments of the present invention, a problem of a conflict miss of a cache in an N-way set associative structure can be resolved without increasing physical hardware overheads, thereby improving a cache hit rate.
Claims17
A cache address mapping method, wherein a cache comprises a plurality of cache sets, and the method comprises:
- obtaining a binary file, the binary file comprising a first hot section, and the first hot section comprising one hot function or comprising a plurality of merged hot functions;
- obtaining alignment information of a second hot section, the second hot section comprising a hot section loaded into the cache, and the alignment information comprises a set index of a last cache set occupied by the second hot section after the second hot section is loaded into the cache;
- and
- performing an offset operation on a storage address of the first hot section based on the alignment information, and mapping the storage address of the first hot section to a cache set with a consecutive set index in the cache, the cache set with the consecutive set index being adjacent to the last cache set, and the storage address of the first hot section comprising a virtual address or a physical address.
A device, comprising:
- a cache comprising a plurality of cache sets;
- and
- a processor in communication with the cache, the processor configured to:
- obtain a binary file, the binary file comprising a first hot section, and the first hot section comprising one hot function or comprising a plurality of merged hot functions;
- obtain alignment information of a second hot section, the second hot section comprising a hot section loaded into the cache, and the alignment information comprises a set index of a last cache set occupied by the second hot section;
- and
- perform an offset operation on a storage address of the first hot section based on the alignment information, and map the storage address of the first hot section to a cache set with a consecutive set index in the cache, the cache set with the consecutive set index being adjacent to the last cache set, and the storage address comprising a virtual address or a physical address.
A non-transitory storage medium storing computer instructions, that when executed by a processor, cause the processor to perform the steps of:
- obtaining a binary file, the binary file comprising a first hot section, and the first hot section comprising one hot function or comprising a plurality of merged hot functions;
- obtaining alignment information of a second hot section, the second hot section comprising a hot section that has been loaded into the cache, and the alignment information comprises a set index of a last cache set occupied by the second hot section;
- and
- performing an offset operation on the storage address of the first hot section based on the alignment information, and mapping the first hot section to a cache set with a consecutive set index in the cache, the cache set with the consecutive set index being adjacent to the last cache set, and the storage address comprising a virtual address or a physical address.
Dependencies are inferred from the claim text.