Electronic circuit and method for clock skew-calibration
AssigneeSamsung Electronics Co., Ltd.
InventorsSethu Mathavan Meikanda Muthu Ayyanar, Tamal Das, Avneesh Singh Verma
Life of this patent
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Abstract
The electronic circuit for multiphase clock skew calibration of at least one example embodiment provides a novel low power solution to detect clock skew errors with very high accuracy, of the order of a few femto seconds, and corrects clock skew errors and decreases and/or minimizes high frequency jitter in a data path of the electronic circuit.
Claims20
An electronic circuit for multi-phase clock skew calibration comprising:
- a filtering circuit configured to filter data output by multi-phase clock-driven serializer circuitry, and generate a differential voltage representative of skew between a plurality of input multi-phase clock signals to the serializer circuitry, wherein a polarity of the differential voltage represents the polarity of skew of the multi-phase clock signals;
- discrete time integrator circuitry configured to amplify the generated differential voltage;
- comparator circuitry configured to determine a divergence of the differential voltage based on the differential voltage and a desired value;
- and
- clock-skew corrector circuitry configured to,
- modify rising edge or falling edge positions of the plurality of multi-phase clock signals based on the determined divergence,
- trigger the serializer circuitry to output data in accordance with the modified plurality of multi-phase clock signals, and
- decrease the skew between the plurality of multi-phase clock signals.
An electronic circuit for multi-phase clock skew-calibration comprising:
- a filtering circuit configured to filter a plurality of multi-phase clock signals, and generate a differential voltage representative of skew between the plurality of multi-phase clock signals;
- discrete time integrator circuitry configured to amplify the generated differential voltage;
- comparator circuitry configured to determine a divergence of the differential voltage based on the differential voltage and a desired value;
- and
- clock-skew corrector circuitry configured to modify rising edge or falling edge positions of the plurality of multi-phase clock signals based on the determined divergence, and decrease the skew between the plurality of multi-phase clock signals.
A process for multi-phase clock skew-calibration in an electronic circuit comprising:
- applying a desired data pattern as input to a multi-phase clock-driven serializer circuitry to determine clock skew information;
- filtering data output by the multi-phase clock-driven serializer circuitry;
- generating a differential voltage representative of skew between a plurality of multi-phase clock signals input to the multi-phase clock-driven serializer circuitry;
- amplifying the generated differential voltage through a discrete time integration;
- determining a divergence of the differential voltage based on the differential voltage and a desired value;
- modifying rising edge and falling edge positions of at least one of the plurality of multi-phase clock signals through clock-skew corrector circuitry based on the determined divergence to decrease the skew between the plurality of clock signals;
- and
- triggering the multi-phase clock-driven serializer circuitry to output data in accordance with the modified at least one clock signal.
Dependencies are inferred from the claim text.