Decoding circuit and decoding method based on Viterbi algorithm

A Viterbi algorithm-based decoding circuit, comprising:

• a Viterbi decoder configured to receive an encoded data and decode the encoded data based on the Viterbi algorithm to generate a decoded data;
• an error correction decoder coupled to the Viterbi decoder and configured to perform error correction on the decoded data to obtain a data content of the encoded data;
• a bit check circuit coupled to the Viterbi decoder and the error correction decoder and configured to compare the decoded data and the data content to generate bit correction information;
• a branch metric calculation circuit configured to calculate a plurality of first branch metrics using the encoded data based on the Viterbi algorithm, the first branch metrics corresponding to a target bit of the data content;
• a branch metric adjustment circuit coupled to the branch metric calculation circuit and configured to adjust at least one of the first branch metrics according to the data content and the bit correction information to generate a plurality of second branch metrics;
• and
• a multiplexer coupled to the branch metric calculation circuit and the branch metric adjustment circuit and configured to select the first branch metrics or the second branch metrics according to the bit correction information.