US 11,251,281 B2Granted

Contact resistance reduction employing germanium overlayer pre-contact metalization

AssigneeIntel Corporation

InventorsGlenn A. Glass, Anand S. Murthy, Tahir Ghani

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Abstract

Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

Claims20

Dependent claims

An integrated circuit structure, comprising:

a fin comprising silicon;
a gate electrode over the fin, the gate electrode having a first side, and the gate electrode having a second side opposite the first side;
a first dielectric spacer along the first side of the gate electrode;
a first source or drain region in the fin proximate the first side of the gate electrode, a portion of the first source or drain region beneath the first dielectric spacer, wherein the first source or drain region comprises silicon and germanium having a germanium concentration graded to a concentration in excess of 50%;
a second dielectric spacer along the second side of the gate electrode;
a second source or drain region in the fin proximate the second side of the gate electrode, a portion of the second source or drain region beneath the second dielectric spacer, wherein the second source or drain region comprises silicon and germanium having a germanium concentration graded to a concentration in excess of 50%;
a dielectric layer over the first source or drain region and over the second source or drain region, the dielectric layer having a first opening exposing only a portion of the first source or drain region, and the dielectric layer having a second opening exposing only a portion of the second source or drain region;
a first germanide layer in the first opening and over the portion of the first source or drain region, the first germanide layer comprising silicon, germanium and titanium;
a second germanide layer in the second opening and over the portion of the second source or drain region, the second germanide layer comprising silicon, germanium and titanium;
a first contact plug in the first opening and on the first germanide layer;
and
a second contact plug in the second opening and on the second germanide layer.

9 more elements

An integrated circuit structure, comprising:

a body comprising silicon;
a gate electrode over the body, the gate electrode having a first side, and the gate electrode having a second side opposite the first side;
a first dielectric spacer along the first side of the gate electrode;
a first source or drain region in the body proximate the first side of the gate electrode, a portion of the first source or drain region beneath the first dielectric spacer, wherein the first source or drain region comprises silicon and germanium having a germanium concentration graded to a concentration in excess of 50%;
a second dielectric spacer along the second side of the gate electrode;
a second source or drain region in the body proximate the second side of the gate electrode, a portion of the second source or drain region beneath the second dielectric spacer, wherein the second source or drain region comprises silicon and germanium having a germanium concentration graded to a concentration in excess of 50%;
a dielectric layer over the first source or drain region and over the second source or drain region, the dielectric layer having a first opening exposing only a portion of the first source or drain region, and the dielectric layer having a second opening exposing only a portion of the second source or drain region;
a first germanide layer in the first opening and over the portion of the first source or drain region, the first germanide layer comprising silicon, germanium and titanium;
a second germanide layer in the second opening and over the portion of the second source or drain region, the second germanide layer comprising silicon, germanium and titanium;
a first contact plug in the first opening and on the first germanide layer;
and
a second contact plug in the second opening and on the second germanide layer.

9 more elements

A computing device, comprising:

a board;
and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a fin comprising silicon;
a gate electrode over the fin, the gate electrode having a first side, and the gate electrode having a second side opposite the first side;
a first dielectric spacer along the first side of the gate electrode;
a first source or drain region in the fin proximate the first side of the gate electrode, a portion of the first source or drain region beneath the first dielectric spacer, wherein the first source or drain region comprises silicon and germanium having a germanium concentration graded to a concentration in excess of 50%;
a second dielectric spacer along the second side of the gate electrode;
a second source or drain region in the fin proximate the second side of the gate electrode, a portion of the second source or drain region beneath the second dielectric spacer, wherein the second source or drain region comprises silicon and germanium having a germanium concentration graded to a concentration in excess of 50%;
a dielectric layer over the first source or drain region and over the second source or drain region, the dielectric layer having a first opening exposing only a portion of the first source or drain region, and the dielectric layer having a second opening exposing only a portion of the second source or drain region;
a first germanide layer in the first opening and over the portion of the first source or drain region, the first germanide layer comprising silicon, germanium and titanium;
a second germanide layer in the second opening and over the portion of the second source or drain region, the second germanide layer comprising silicon, germanium and titanium;
a first contact plug in the first opening and on the first germanide layer;
and
a second contact plug in the second opening and on the second germanide layer.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/881,541Filed 22 May 2020 · continuation
Priority: 21 Dec 2010
Published: US 2020/0287011 A110 Sep 2020
Granted: 15 Feb 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification48 codes

H10D 62/122
Nanowire, nanosheet or nanotube semiconductor bodies: oriented at angles to substrates, e.g. perpendicular to substrates
H10D 30/019
Manufacture or treatment: of FETs having stacked nanowire, nanosheet or nanoribbon channels
H10D 30/021
Manufacture or treatment: of FETs having insulated gates [IGFET]
H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…

Family

Application12/975,278Parent of this continuation-in-part · filed 21 Dec 2010
PCT/US2011/054198Parent of this continuation · filed 30 Sep 2011
US 8,901,537 B2Parent of this continuation-in-part · filed 2 Dec 2014
Application14/673,143Parent of this continuation · filed 30 Mar 2015
US 8,994,104 B2Parent of this continuation · filed 31 Mar 2015
Application15/339,308Parent of this continuation · filed 31 Oct 2016
US 9,484,432 B2Parent of this continuation · filed 1 Nov 2016
Application16/416,445Parent of this continuation · filed 20 May 2019
US 10,297,670 B2Parent of this continuation · filed 21 May 2019
US 2020/0287011 A1Pre-grant publication · published 10 Sep 2020
US 10,700,178 B2Parent of this continuation
Application13/990,224Parent of this continuation
Application13/990,224Parent of this continuation-in-part
US 2012/0153387 A1Published application
US 2013/0248999 A1Published application
US 2015/0206942 A1Published application
US 2017/0047419 A1Published application
US 2019/0341464 A1Published application
US 11,251,281 B2This patent

From the US filing history. Foreign family members aren’t listed.