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US 11,249,724 B1Granted
Processing-memory architectures performing atomic read-modify-write operations in deep learning systems
AssigneeHabana Labs Ltd.
InventorsShlomo Raikin, Ron Shalev, Sergei Gofman, Ran Halutz, Nadav Klein
Life of this patent
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Abstract
A computational apparatus includes a memory unit and Read-Modify-Write (RMW) logic. The memory unit is configured to hold a data value. The RMW logic, which is coupled to the memory unit, is configured to perform an atomic RMW operation on the data value stored in the memory unit.
Claims20
A processing-memory circuit, comprising:
- a data input interface, configured to receive a sequence of input data values for a data reduction operation;
- an operation unit, configured to apply the data reduction operation;
- a memory element, which is identified by an address;
- and
- Read-Modify-Write (RMW) logic, which is coupled to the memory element and to the operation unit, and is configured to perform a sequence of iterations including, in each iteration, atomically (i) reading a previous result of the data reduction operation from the address, (ii) applying the data reduction operation to the previous result and to a next input data value using the operation unit, thereby generating a next result, and (iii) writing the next result of the data reduction operation back to the address,
- wherein the RMW logic comprises:
- a demultiplexer connected to input the previous result from the memory element to the operation unit and to output the previous result from the circuit;
- and
- a multiplexer connected to input the next result from the operation unit to the memory element, so as to serve as the previous result in a next iteration in the sequence.
6 more elements
A method, comprising:
- receiving a sequence of input data values for a data reduction operation;
- and
- performing a sequence of iterations using Read-Modify-Write (RMW) logic, which is coupled to a memory element that is identified by an address and to an operation unit that is configured to apply the data reduction operation, including, in each iteration, atomically (i) reading a previous result of the data reduction operation from the address, (ii) applying the data reduction operation to the previous result and to a next input data value using the operation unit, thereby generating a next result, and (iii) writing the next result of the data reduction operation back to the address,
- wherein the RMW logic comprises:
- a demultiplexer connected to input the previous result from the memory element to the operation unit and to output the previous result from the circuit;
- and
- a multiplexer connected to input the next result from the operation unit to the memory element, so as to serve as the previous result in a next iteration in the sequence.
4 more elements
Dependencies are inferred from the claim text.