Wideband passive buffer with DC level shift for wired data communication

A wideband communication circuit comprising:

• a passive buffer circuit with input terminals to receive input signals and output terminals to transmit output signals;
• and
• a continuous-time linear equalizer (CTLE) with a plurality of input transistors connected to the output terminals of the passive buffer circuit to equalize the output signals from the passive buffer circuit,
• wherein the passive buffer circuit comprises:
• a plurality of buffer elements connected between the input terminals of the passive buffer circuit and the output terminals of the passive buffer circuit, the output terminals of the passive buffer circuit being connected to input terminals of the CTLE, each of the buffer elements providing a first path with a resistor and a second path with a series-connected capacitor and inductor for signals from the input terminals of the passive buffer circuit to the input terminals of the CTLE;
• a plurality of current sources connected between the output terminals and at least one fixed voltage;
• and
• a feedback loop from the input transistors of the CTLE to the current sources to control direct current (DC) voltage at each of the input terminals of the CTLE, the feedback loop including an error amplifier that controls the current sources based on voltages on the input transistors of the CTLE with respect to a reference voltage.

A passive buffer circuit comprising:

• first and second buffer elements connected between first and second input terminals of the passive buffer circuit and first and second output terminals of the passive buffer circuit, the first and second output terminals of the passive buffer circuit being connected to input terminals of a communication component circuit with first and second input transistors, each of the first and second buffer elements providing a first path with a resistor and a second path with a series-connected capacitor and inductor for signals from the first and second input terminals of the passive buffer circuit to the input terminals of the communication component circuit;
• first and second current sources connected between the first and second output terminals and at least one fixed voltage;
• and
• a feedback loop from the first and second input transistors of the communication component circuit to the current sources to control direct current (DC) voltage at each of the inputs of the communication component circuit, the feedback loop including an error amplifier and first and second feedback loop resistors, the first feedback loop resistor being connected to the first input transistor of the communication component circuit and to a first input of the error amplifier, the second feedback loop resistor being connected to the second input transistor of the communication component circuit and to the first input of the error amplifier, wherein a voltage on the first input of the error amplifier is compared to a reference voltage on a second input of the error amplifier to output an error signal to control the current sources based on voltages on the first and second input transistors of the communication component circuit with respect to the reference voltage.