Back to results
US 11,245,402 B2Granted
Matrix phase interpolator for phase locked loop
AssigneeKandou Labs, S.A.
InventorArmin Tajalli
Life of this patent
Estimating the term…
Abstract
Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.
Claims20
A method comprising:
- obtaining a plurality of phases of a reference clock signal and a plurality of phases of a local oscillator signal;
- generating, using at least two sets of comparators, at least two sets of phase-error signals, each respective set of phase-error signals being associated with a fixed phase offset and wherein each set of phase-error signals comprises comparisons of the plurality of phases of the reference clock signal to corresponding phases of the local oscillator signal having the fixed phase offset;
- selecting sets of phase-error signals having adjacent fixed phase offsets;
- applying respective weighting factors to each of the selected sets of phase-error signals, the respective weighting factors associated with an intermediate phase in between the adjacent fixed phase offsets of the selected sets of phase-error signals;
- generating, using a summation circuit, a composite phase-error signal by forming a summation of the selected sets of phase-error signals;
- and
- providing the composite phase-error signal to a local oscillator generating the plurality of phases of the local oscillator signal.
4 more elements
An apparatus comprising:
- a matrix phase comparator configured to obtain a plurality of phases of a reference clock signal and a plurality of phases of a local oscillator signal, the matrix phase comparator configured to:
- generate, using at least two sets of comparators, at least two sets of phase-error signals, each respective set of phase-error signals being associated with a fixed phase offset and wherein each set of phase-error signals comprises comparisons of the plurality of phases of the reference clock signal to corresponding phases of the local oscillator signal having the fixed phase offset;
- select sets of phase-error signals having adjacent fixed phase offsets;
- and
- apply respective weighting factors to each of the selected sets of phase-error signals, the respective weighting factors associated with an intermediate phase in between the adjacent fixed phase offsets of the selected sets of phase-error signals;
- and
- a summation circuit configured to generate a composite phase-error signal by forming a summation of the selected sets of phase-error signals, and to provide the composite phase-error signal to a local oscillator generating the plurality of phases of the local oscillator signal.
4 more elements
Dependencies are inferred from the claim text.