Low temperature bonded structures
AssigneeInvensas Bonding Technologies, Inc.
InventorsCyprian Emeka Uzoh, Jeremy Alfred Theil, Rajesh Katkar, Guilian Gao, Laura Wills Mirkarimi
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Abstract
Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second conductive interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.
Claims24
A microelectronic assembly, comprising:
- a first substrate having a bonding surface, the bonding surface of the first substrate having a planarized topography;
- a first plurality of metallic features at the bonding surface of the first substrate;
- a first recessed portion disposed in a surface of one or more of the first plurality of metallic features and extending a preselected depth below the bonding surface of the first substrate, the first recessed portion at least partially filled with a first material different than a conductive material of the first plurality of metallic features;
- a second substrate having a bonding surface, the bonding surface of the second substrate having a planarized topography and bonded to the bonding surface of the first substrate;
- and
- a second plurality of metallic features at the bonding surface of the second substrate and bonded to the first plurality of metallic features, either or both of the first plurality of metallic features and the second plurality of metallic features comprising two or more materials, including at least one non-barrier conductive material or silicon-containing material provided over an underlying conductive material of the first or second plurality of metallic features.
A microelectronic assembly, comprising:
- a first substrate having a surface and a first conductive structure comprising a first conductive feature and a first element;
- a second substrate having a surface and a second conductive structure, the surface of the first substrate intimately bonded to the surface of the second substrate, and the first conductive structure bonded to the second conductive structure;
- and
- a fill region coupling the first conductive structure to the second conductive structure, wherein the fill region includes the first element, the first element having a melting point higher than a melting point of the first conductive feature or portions of the second conductive structure.
A microelectronic assembly, comprising:
- a first substrate having a surface and a first conductive structure comprising a first element;
- a second substrate having a surface and a second conductive structure, the surface of the first substrate intimately bonded to the surface of the second substrate, and the first conductive structure bonded to the second conductive structure;
- and
- a fill region comprising the first element coupling the first conductive structure to the second conductive structure, the first element including polysilicon, wherein the fill region is a discontinuous layer.
A microelectronic assembly, comprising:
- a first substrate having a surface and a first conductive structure comprising a first element;
- a second substrate having a surface and a second conductive structure, the surface of the first substrate intimately bonded to the surface of the second substrate, and the first conductive structure bonded to the second conductive structure;
- and
- a first fill region comprising the first element coupling the first conductive structure to the second conductive structure, wherein the first conductive structure bonded to the second conductive structure contains one or more voids.
Dependencies are inferred from the claim text.