Apparatus and method for scaling pre-scaled results of complex multiply-accumulate operations on packed real and imaginary data elements

A processor comprising:

• a decoder to decode a first instruction to generate a decoded instruction;
• a first source register to store a first plurality of packed N-bit real and imaginary data elements;
• a second source register to store a second plurality of packed M-bit real and imaginary data elements;
• a third source register to store a third plurality of packed N-bit real and imaginary data elements;
• execution circuitry to execute the decoded instruction, the execution circuitry comprising:
• multiplier circuitry to multiply packed real N-bit data elements in the first source register with packed imaginary M-bit data elements in the second source register and to multiply packed imaginary N-bit data elements in the first source register with packed real M-bit data elements in the second source register to generate at least four imaginary products;
• adder circuitry to add a first selected imaginary product and a second selected imaginary product to generate a first temporary result and to add a third selected imaginary product and a fourth selected imaginary product to generate a second temporary result, the adder circuitry to add the first temporary result to a first packed N-bit data element from the third source register to generate a first pre-scaled result, to subtract the first temporary result from the first packed N-bit data element to generate a second pre-scaled result, to add the second temporary result to a second packed N-bit data element from the third source register to generate a third pre-scaled result, and to subtract the second temporary result from the second packed N-bit data element to generate a fourth pre-scaled result;
• and
• scaling circuitry for scaling the first, second, third and fourth pre-scaled results to a specified bit width to generate first, second, third, and fourth final results;
• and
• a destination register to store the first, second, third, and fourth final results in specified data element positions.

A method comprising:

• decoding a first instruction to generate a decoded instruction;
• storing a first plurality of packed N-bit real and imaginary data elements in a first source register;
• storing a second plurality of packed M-bit real and imaginary data elements in a second source register;
• storing a third plurality of packed N-bit real and imaginary data elements in a third source register;
• multiplying packed real N-bit data elements in the first source register with packed real M-bit data elements in the second source register;
• multiplying packed imaginary N-bit data elements in the first source register with packed imaginary M-bit data elements in the second source register to generate at least four real products;
• subtracting a first selected real product from a second selected real product to generate a first temporary result and subtracting a third selected real product from a fourth selected real product to generate a second temporary result;
• adding the first temporary result to a first packed N-bit data element from the third source register to generate a first pre-scaled result, subtracting the first temporary result from the first packed N-bit data element to generate a second pre-scaled result, adding the second temporary result to a second packed N-bit data element from the third source register to generate a third pre-scaled result, and subtracting the second temporary result from the second packed N-bit data element to generate a fourth pre-scaled result;
• scaling the first, second, third and fourth pre-scaled results to a specified bit width to generate first, second, third, and fourth final results;
• and
• storing the first, second, third, and fourth final results in specified data element positions.

A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of:

• decoding a first instruction to generate a decoded instruction;
• storing a first plurality of packed N-bit real and imaginary data elements in a first source register;
• storing a second plurality of packed M-bit real and imaginary data elements in a second source register;
• storing a third plurality of packed N-bit real and imaginary data elements in a third source register;
• multiplying packed real N-bit data elements in the first source register with packed real M-bit data elements in the second source register;
• multiplying packed imaginary N-bit data elements in the first source register with packed imaginary M-bit data elements in the second source register to generate at least four real products;
• subtracting a first selected real product from a second selected real product to generate a first temporary result and subtracting a third selected real product from a fourth selected real product to generate a second temporary result;
• adding the first temporary result to a first packed N-bit data element from the third source register to generate a first pre-scaled result, subtracting the first temporary result from the first packed N-bit data element to generate a second pre-scaled result, adding the second temporary result to a second packed N-bit data element from the third source register to generate a third pre-scaled result, and subtracting the second temporary result from the second packed N-bit data element to generate a fourth pre-scaled result;
• scaling the first, second, third and fourth pre-scaled results to a specified bit width to generate first, second, third, and fourth final results;
• and
• storing the first, second, third, and fourth final results in specified data element positions.