Networks and hierarchical routing fabrics with heterogeneous memory structures for scalable event-driven computing systems

A neural network circuit, which comprises a plurality of tiles/chips (6);

• the tiles/chips (6) comprising a plurality of cores (10), the core (10) comprising at least one neuron circuit (90) that simulates biological neuron and at least one synapse circuit (80) that simulates synapse;
• the neuron circuit (90) integrates multiple events received and accepted by the corresponding synapse circuits (80), and generates a spike event when the integrated signal crosses the trigger threshold;
• its characteristics are:
• the core (10) also includes:
• a core router R1 for providing circuit connectivity within the core;
• the tile/chip (6) further includes:
• a chip router R2 for providing connectivity between the cores and a mesh router R3 for providing connectivity between the tiles/chips (6);
• wherein, the core router R1 transmits or/and receives events to the chip router R2, and the chip router R2 transmits or/and receives events to the mesh router R3;
• on one tile/chip (6), the core router R1, the chip router R2 and the mesh router R3 form a tree structure;
• the mesh router R3 is arranged in a two-dimensional mesh;
• each tile/chip (6) has one mesh router R3, and the mesh router R3 interconnects the tree structure in the two-dimensional mesh;
• a broadcast driver (7), which is configured to broadcast to synapse array (8) through the broadcast driver (7) after the core router R1 receives an event, and the synapse array (8) has a plurality of said synapse circuits (80).