Systems, methods, and devices for high-speed data modulation

A data modulator for a transmitter, the data modulator comprising:

• a multiplexer configured to:
• receive, at a first rate, a first data stream including a plurality of first symbols and a second data stream including a plurality of second symbols;
• and
• selectively output, based on a first clock signal, the plurality of first symbols and the plurality of second symbols to form a third data stream that achieves a second rate greater than the first rate for transmission of the third data stream by the transmitter,
• wherein the multiplexer is configured to output a first subset of the plurality of first symbols during a first half of a period of the first clock signal, and output a second subset of the plurality of second symbols during a second half of the period of the first clock signal.

A digital to analog converter (DAC), comprising:

• a first amplifier block configured to receive a first bit and a second bit of a first data stream at a first rate and output first and second signals based on values of the first and second bits;
• a second amplifier block configured to receive a third bit and a fourth bit of a second data stream at the first rate and output third and fourth signals based on values of the third and fourth bits;
• a modulator configured to receive the first, second, third, and fourth signals, and selectively output, based on a first clock signal, symbols of the first, second, third, and fourth signals to form a third data stream having a second rate greater than the first rate;
• and
• a conversion circuit configured to receive the symbols of the third data stream and output an analog signal representative of the first data stream and the second data stream.

A transmitter, comprising:

• a parallel input serial output (PISO) device configured to receive parallel input data and output serialized data at a first rate;
• and
• a digital to analog (DAC) converter including:
• a first amplifier block configured to receive first and second bits of a first data stream of the serialized data at the first rate and output first and second signals based on values of the first and second bits;
• a second amplifier block configured to receive third and fourth bits of a second data stream of the serialized data at the first rate and output third and fourth signals based on values of the third and fourth bits, wherein the first, second, third and fourth bits of data are received by the first and second amplifier blocks according to a predetermined arrangement;
• a modulator configured to receive the first, second, third, and fourth signals, and to selectively output, based on a first clock signal, symbols of the first, second, third, and fourth signals to form a third data stream having a second rate greater than the first rate;
• and
• a conversion circuit configured to receive the symbols of the third data stream from the modulator and output an analog signal representative of the third data stream.