C-PHY half-rate wire state encoder and decoder

A data communication apparatus comprising:

• a plurality of line drivers configured to couple the data communication apparatus to a 3-wire link;
• a first wire state encoder configured to receive a first symbol in a sequence of symbols when the 3-wire link is in a first signaling state, and to define a second signaling state for the 3-wire link based on the first symbol and the first signaling state;
• a second wire state encoder configured to receive a second symbol in the sequence of symbols, and to define a third signaling state for the 3-wire link based on the second symbol and the second signaling state, wherein the first symbol immediately precedes the second symbol in the sequence of symbols, wherein the 3-wire link transitions from the first signaling state to the second signaling state and from the second signaling state to the third signaling state in consecutive symbol transmission intervals, and wherein signaling states of at least one wire in the 3-wire link changes when the 3-wire link transitions from the second signaling state to the third signaling state;
• and
• an equalizer circuit configured to receive delayed versions of the second signaling state and the third signaling state, and to configure the plurality of line drivers when initiating transmission of the third signaling state based on differences between the second signaling state and the third signaling state.

A data communication method, comprising:

• configuring a plurality of line drivers to be coupled to a 3-wire link;
• receiving a first symbol in a sequence of symbols at a first wire state encoder when the 3-wire link is in a first signaling state;
• defining a second signaling state for the 3-wire link based on the first symbol and the first signaling state;
• receiving a second symbol in the sequence of symbols at a second wire state encoder;
• defining a third signaling state for the 3-wire link based on the second symbol and the second signaling state, wherein the first symbol immediately precedes the second symbol in the sequence of symbols, wherein the 3-wire link transitions from the first signaling state to the second signaling state and from the second signaling state to the third signaling state in consecutive symbol transmission intervals, and wherein signaling states of at least one wire in the 3-wire link changes when the 3-wire link transitions from the second signaling state to the third signaling state;
• providing a half-rate symbol clock signal that has a period twice a duration of each symbol transmission interval;
• and
• selecting between the second signaling state and the third signaling state to provide wire state information to a driver control circuit that controls the plurality of line drivers, wherein selection is based on phase of the half-rate symbol clock signal.

A non-transitory processor-readable storage medium comprising code for:

• configuring a plurality of line drivers to be coupled to a 3-wire link;
• receiving a first symbol in a sequence of symbols at a first wire state encoder when the 3-wire link is in a first signaling state;
• defining a second signaling state for the 3-wire link based on the first symbol and the first signaling state;
• receiving a second symbol in the sequence of symbols at a second wire state encoder;
• defining a third signaling state for the 3-wire link based on the second symbol and the second signaling state, wherein the first symbol immediately precedes the second symbol in the sequence of symbols, wherein the 3-wire link transitions from the first signaling state to the second signaling state and from the second signaling state to the third signaling state in consecutive symbol transmission intervals, and wherein signaling states of at least one wire in the 3-wire link changes when the 3-wire link transitions from the second signaling state to the third signaling state;
• providing a half-rate symbol clock signal that has a period twice a duration of each symbol transmission interval;
• and
• selecting between the second signaling state and the third signaling state to provide wire state information to a driver control circuit that controls the plurality of line drivers, wherein selection is based on phase of the half-rate symbol clock signal.