SerDes receiver with optimized CDR pulse shaping

A clock data recovery method comprising:

• receiving a first input signal from an analog to digital controller;
• equalizing the first input signal based on a plurality of received tap coefficients to generate a first output signal;
• adding the first output signal and a feedback signal originating from a decision feedback equalizer to generate a second output signal;
• providing an initial set of tentative decisions to a decision feedforward equalizer;
• providing an equalized output signal by the decision feedforward equalizer;
• generating an error signal based on the equalized output signal from the decision feedforward equalizer, wherein the plurality of received tap coefficients are based on the error signal;
• and
• providing an adjustment signal to the analog to digital controller based on the first output signal.