Systems and methods for timing recovery with bandwidth extension
AssigneeMarvell Asia Pte Ltd
InventorsBenjamin P. Smith, Jamal Riani
Life of this patent
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Abstract
The present invention is directed to circuits and communication. More specifically, a specific embodiment of the present invention provides a timing recovery device with two stages. The first stage generates a clock signal to sample the received waveform, and the second stage provides timing-jitter mitigation. The second stage includes a jitter mitigation circuit with coefficients a function of the instantaneous jitter estimate, in addition to a jitter estimation tracking loop consisting of an error generator, a timing error detector and a loop filter to compensate for timing jitter associated with the clock signal. There are other embodiments as well.
Claims19
A timing recovery apparatus comprising:
- a first stage circuit comprising:
- an analog-to-digital converter (ADC), an equalizer, and an oscillator;
- the ADC being configured to digitize a data stream using a sampler triggered by a recovered clock signal and to adjust an operating frequency based on a timing correction signal generated by the oscillator, the recovered clock signal being impaired by a residual timing jitter;
- and the equalizer being configured to provide equalized data based on an output of the ADC;
- and
- a second stage circuit comprising:
- a jitter mitigation circuit coupled to the equalizer and configured to compensate for timing-jitter-induced inter-symbol interference (ISI) in an equalizer output, the jitter mitigation circuit having coefficients associated with an estimate of the residual timing jitter;
- and
- a jitter estimation circuit configured to determine the residual timing jitter, the jitter estimation circuit comprising:
- an error generator configured to generate an error signal based at least on a detector output signal;
- a timing error detector (TED) configured to generate a timing error signal based at least on the error signal;
- a selector coupled to the TED, the selector being coupled to an intermediate output of the jitter mitigation circuit and a data detector signal;
- and
- a loop filter configured to generate the estimate of the residual timing jitter based on the timing error signal.
A circuit for jitter mitigation and timing recovery, the circuit comprising:
- a jitter mitigation circuit coupled to an equalizer to compensate for timing-jitter-induced inter-symbol interference (ISI) in an equalizer output, the jitter mitigation circuit comprising a finite impulse response filter with taps that depend on an estimate of a residual timing jitter, the estimate of the residual timing jitter being provided by a jitter tracking loop;
- an error generator configured to generate an error signal based on an output of the jitter mitigation circuit and a detector output signal;
- a timing error detector (TED) configured to generate a timing error signal;
- a selector coupled to the TED, the selector being coupled to an intermediate output of the jitter mitigation circuit and a data detector signal;
- and
- a loop filter configured to generate the estimate of the residual timing jitter based on the timing error signal.
A receiver apparatus comprising:
- an interface for receiving a data stream;
- and
- a timing recovery module comprising a first stage circuit and a second stage circuit;
- wherein:
- the first stage circuit comprises:
- an analog-to-digital converter (ADC), the ADC being configured to digitize the data stream using a recovered clock signal, the recovered clock signal being impaired by residual timing jitter,
- an equalizer configured to provide equalized data based on an output of the ADC;
- and
- the second stage circuit comprising a jitter mitigation circuit coupled to the equalizer and configured to compensate for timing-jitter-induced inter-symbol interference (ISI) in an equalizer output, the jitter mitigation circuit comprising a finite impulse response filter with taps that depend on an estimate of a residual timing jitter, the estimate of the residual timing jitter being provided by a jitter tracking loop, the jitter mitigation circuit comprising a selector coupled to an intermediate output of the jitter mitigation circuit and a detector signal.
Dependencies are inferred from the claim text.