Error correction circuit and operating method thereof
AssigneeSK hynix Inc.
InventorJang Seob Kim
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Abstract
Disclosed are devices, systems and methods for error correction decoding using an iterative decoding scheme. An error correction circuit includes a node processor to perform a plurality of iterations for updating values of one or more variable nodes and one or more check nodes using initial values assigned to the one or more variable nodes, respectively, a trapping set detector to detect a trapping set in at least one of the plurality of iterations by applying a predetermined trapping set determination policy, and a post processor to reduce at least one of the initial values or invert at least one of values of the variable nodes corresponding to an iteration in which the trapping set is detected, upon detection of the trapping set.
Claims20
An error correction circuit to perform error correction decoding using an iterative decoding scheme, comprising:
- a node processor to perform a plurality of iterations to update values of one or more variable nodes and one or more check nodes using initial values assigned to the one or more variable nodes, respectively;
- a trapping set detector to detect a trapping set in at least one of the plurality of iterations by applying a predetermined trapping set determination policy;
- and
- a post processor to change at least one of the initial values of the variable nodes corresponding to an iteration in which the trapping set is detected, upon detection of the trapping set.
An error correction circuit to perform error correction decoding using an iterative decoding scheme, comprising:
- a node processor to perform a plurality of iterations to update values of one or more variable nodes and one or more check nodes using initial values assigned to the one or more variable nodes, respectively;
- a trapping set detector to detect a trapping set in at least one of the plurality of iterations by applying a predetermined trapping set determination policy;
- and
- a post processor to reduce at least one of the initial values corresponding to an iteration in which the trapping set is detected, upon detection of the trapping set.
An error correction circuit to perform error correction decoding using an iterative decoding scheme, comprising:
- a node processor to perform a plurality of iterations to update values of one or more variable nodes and one or more check nodes using initial values assigned to the one or more variable nodes, respectively;
- a trapping set detector to detect a trapping set in at least one of the plurality of iterations by applying a predetermined trapping set determination policy;
- and
- a post processor to invert at least one of values of the variable nodes corresponding to an iteration in which the trapping set is detected, upon detection of the trapping set.
Dependencies are inferred from the claim text.