Calibration of digital-to-analog converter with low pin count
AssigneeCirrus Logic, Inc.
InventorJohn L. Melanson
Life of this patent
Estimating the term…
Abstract
An open-loop digital-to-analog converter (DAC) circuit may include a delta-sigma modulator, a decode block responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, an analog output driver responsive to the plurality of DAC elements, a test signal generator configured to generate a test signal that is responsive to inputs of the plurality of DAC elements, and a synchronizer configured to enable replication of the test signal at an external test system coupled to the open-loop DAC circuit in order to generate a matching test signal at the external test system that matches the test signal generated by the test signal generator.
Claims18
An open-loop digital-to-analog converter (DAC) circuit, comprising:
- a delta-sigma modulator;
- a decode block responsive to the delta-sigma modulator configured to perform a DAC decode operation;
- a plurality of DAC elements responsive to the DAC decode operation;
- an analog output driver responsive to the plurality of DAC elements;
- a test signal generator configured to generate a test signal that is responsive to an input of the delta-sigma modulator;
- and
- a synchronizer configured to enable replication of the test signal at an external test system coupled to the open-loop DAC circuit in order to generate a matching test signal at the external test system that matches the test signal generated by the test signal generator.
A method comprising, in an open-loop digital-to-analog converter (DAC) circuit having a delta-sigma modulator, a decode block responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, and an analog output driver responsive to the plurality of DAC elements:
- generating a test signal that is responsive to an input of the delta-sigma modulator;
- and
- enabling replication of the test signal at an external test system coupled to the open-loop DAC circuit in order to generate a matching test signal at the external test system that matches the test signal.
An external test system for an open-loop digital-to-analog converter (DAC) circuit having a delta-sigma modulator, a decode block responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, an analog output driver responsive to the plurality of DAC elements, a test signal generator configured to generate a test signal that is responsive to an input of the delta-sigma modulator, and a synchronizer configured to enable replication of the test signal at an external test system coupled to the open-loop DAC circuit in order to generate a matching test signal at the external test system that matches the test signal generated by the test signal generator, wherein the external test system comprises:
- a matched delta-sigma modulator matched to the delta-sigma modulator and responsive to the matching test signal;
- and
- a matched decode block matched to the decode block and responsive to the matched delta-sigma modulator and configured to perform a second DAC decode operation matched to the DAC decode operation.
A method for an external test system for an open-loop digital-to-analog converter (DAC) circuit having a delta-sigma modulator, a decode block responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, an analog output driver responsive to the plurality of DAC elements, a test signal generator configured to generate a test signal that is responsive to an input of the delta-sigma modulator, and a synchronizer configured to enable replication of the test signal at an external test system coupled to the open-loop DAC circuit in order to generate a matching test signal at the external test system that matches the test signal generated by the test signal generator, wherein the method comprises:
- matching a matched delta-sigma modulator to the delta-sigma modulator and responsive to the matching test signal;
- and
- matching a matched decode block to the decode block and responsive to the matched delta-sigma modulator and configured to perform a second DAC decode operation matched to the DAC decode operation.
Dependencies are inferred from the claim text.