Error compensation correction system and method for analog-to-digital converter with time interleaving structure

An error compensation correction system for an analog-to-digital converter with a time interleaving structure, comprising an analog-to-digital converter with a time interleaving structure, and further comprising a master clock module, a packet clock module, an error correction module, an adaptive processing module and an overall multiplexer (MUX) circuit;

• the analog-to-digital converter with a time interleaving structure includes a plurality of sub-ADCs with a same structure, the sub-ADCs are packeted, a number of the packet clock modules is the same as a packet number of the sub-ADCs, and each packet of sub-ADCs is respectively connected to a corresponding packet clock module;
• the master clock module generates a packet master clock;
• each packet clock module is connected to the master clock module, and an operation clock of the sub-ADC in the packet and a packet channel clock selection signal are obtained through the packet clock module connected with the packet;
• the error correction module corrects the analog-to-digital converter according to a correction parameter;
• the adaptive processing module estimates bias, gain, and clock phase errors between the packets according to data corrected by the error correction module, and updates the correction parameter;
• the overall MUX circuit synthesizes corrected data of each packet into system output data according to a phase order of corresponding packet master clock.