Leakage compensation for a successive approximation analog-to-digital converter

An analog-to-digital conversion circuit, comprising:

• a switched-capacitor successive-approximation-register (SAR), analog-to-digital converter (ADC), configured to receive an analog input signal and a clock signal, to sample the analog input signal, and to generate a sequence of digital output words corresponding to samples of the analog input signal, wherein the SAR-ADC is configured to generate a bit of a digital output word per cycle of the clock signal;
• a clock-signal generator configured to supply the clock signal to the SAR-ADC;
• and
• a post-processing unit configured to receive the sequence of digital output words and generate a sequence of digital output numbers, corresponding to the digital output words, based on bit weights assigned to the bits of the digital output words, wherein the post-processing unit is configured to determine a parameter representative of a time constant for a decay of a signal level in the SAR-ADC, and determine the bit weights based on said parameter.

A receiver circuit comprising an analog-to-digital conversion circuit, wherein the analog-to-digital conversion circuit comprises:

• a switched-capacitor successive-approximation-register (SAR), analog-to-digital converter (ADC), configured to receive an analog input signal and a clock signal, to sample the analog input signal, and to generate a sequence of digital output words corresponding to samples of the analog input signal, wherein the SAR-ADC is configured to generate a bit of a digital output word per cycle of the clock signal;
• a clock-signal generator configured to supply the clock signal to the SAR-ADC;
• a control unit configured to control a rate of the clock signal;
• and
• a post-processing unit configured to receive the sequence of digital output words and generate a sequence of digital output numbers, corresponding to the digital output words, based on bit weights assigned to the bits of the digital output words, wherein the bit weights depend on the rate of the clock signal, wherein the post-processing unit is configured to determine a parameter representative of a time constant for a decay of a signal level in the SAR-ADC, and determine the bit weights based on said parameter.

A communication apparatus comprising a receiver circuit, wherein the receiver circuit comprises an analog-to-digital conversion circuit, wherein the analog-to-digital conversion circuit comprises:

• a switched-capacitor successive-approximation-register (SAR), analog-to-digital converter (ADC), configured to receive an analog input signal and a clock signal, to sample the analog input signal, and to generate a sequence of digital output words corresponding to samples of the analog input signal, wherein the SAR-ADC is configured to generate a bit of a digital output word per cycle of the clock signal;
• a clock-signal generator configured to supply the clock signal to the SAR-ADC;
• a control unit configured to control a rate of the clock signal;
• and
• a post-processing unit configured to receive the sequence of digital output words and generate a sequence of digital output numbers, corresponding to the digital output words, based on bit weights assigned to the bits of the digital output words, wherein the bit weights depend on the rate of the clock signal, wherein the post-processing unit is configured to determine a parameter representative of a time constant for a decay of a signal level in the SAR-ADC, and determine the bit weights based on said parameter.