Locked loop circuit and method with multi-phase synchronization

A locked-loop circuit, comprising:

• phase synchronization circuitry to synchronize a DCO clock phase to a reference clock phase, the phase synchronization circuitry including
• sampling circuitry to sequentially sample the reference clock with each of N sampling clocks having offset phases, a first one of the N sampling clocks comprising a master sampling clock;
• edge detection logic to accumulate phase information from the multiple sampling clocks and determine, based on the accumulated phase information, whether any of the sampling clocks other than the master sampling clock correspond to edge detection signals that occurred early with respect to a rising edge of the master sampling clock;
• index logic to generate index values for any of the determined early edge detection signals, each index value corresponding to a phase difference between the master sampling clock phase and a given sampling clock phase associated with a corresponding early edge detection signal, the index logic to transfer the generated index values to a master phase transfer logic unit;
• and
• phase adjust logic to adjust the master clock phase based on a selected one of the generated index values.

A phase synchronization circuit for use in a phase-locked loop (PLL) circuit, comprising:

• sampling circuitry to sequentially sample a reference clock with each of N sampling clocks having offset phases, a first one of the N sampling clocks comprising a master sampling clock;
• edge detection logic to accumulate phase information from the multiple sampling clocks and determine, based on the accumulated phase information, whether any of the sampling clocks other than the master sampling clock correspond to edge detection signals that occurred early with respect to a rising edge of the master sampling clock;
• index logic to generate index values for any of the determined early edge detection signals, each index value corresponding to a phase difference between the master sampling clock phase and a given sampling clock phase associated with a corresponding early edge detection signal, the index logic to transfer the generated index values to a master phase transfer logic unit;
• and
• phase adjust logic to adjust the master clock phase based on a selected one of the generated index values.