Variable-length clock stretcher with correction for glitches due to phase detector offset
AssigneeSambaNova Systems, Inc.
InventorsFahim ur Rahman, Jin-Uk Shin
Life of this patent
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Abstract
A clock stretcher includes a DLL that derives delayed versions of an input clock signal, and a combiner that cyclically selects the delayed versions to generate a modified clock signal. The combiner uses a hop code, dependent on a sensed condition, to determine the step size for the cyclical selection. The DLL may have a phase error that would cause a glitch in the modified clock during phase selection wraparound. The clock stretcher proactively increases the step size during wraparound by adding an offset skip parameter value to the hop code. The clock stretcher may operate from a sensed power supply without intervening voltage regulation.
Claims19
A method to correct glitches due to phase detector offset in a clock stretcher, wherein the clock stretcher receives input clock pulses with a clock cycle time T on an input and delivers pulses of a modified clock on an output, the method comprising the following steps:
- delaying the input clock pulses in a delay line including delay stages in a DLL;
- receiving a required length value N1 that may be changed in runtime;
- determining an end-of-chain (EOC) value for an input clock pulse traveling through the delay line;
- in the DLL, locking a delay of N1 delay stages to the clock cycle time T and forwarding N1 phases of the delayed input clock pulses to a combiner;
- cyclically selecting and coupling at least one of the N1 phases with the clock stretcher output to obtain the modified clock, wherein a phase selection step size for successive modified clock pulses is determined by a hop code h that is dependent on a sensed condition;
- retrieving an offset skip parameter value os;
- and
- using the offset skip parameter value os during a phase selection wraparound to correct for a phase detector offset glitch.
A clock stretcher comprising:
- a clock input configured for receiving an input clock;
- a required length input configured for receiving a parameter N1;
- a delay-locked loop (DLL) including a delay line with two or more delay stages, wherein:
- a delay line input is electrically coupled with the clock input;
- a DLL phase comparator and a DLL loop filter operate at a speed slower than the input clock;
- the DLL is operable to lock a delay of an active part of the delay line to a duration of a cycle of the input clock;
- and
- the active part of the delay line has a length of N1 delay stages;
- an end-of-chain (EOC) detector, operable to detect a clock signal pulse edge present on at least a part of the delay stages, and to provide an EOC number associated with a delay stage in which the clock pulse edge is detected;
- a control unit operable to:
- receive the parameter N1, a hop code h, and an offset skip value os;
- output a combiner control signal including a combiner address based on a cyclical selection of N1 delay line phase output signals, wherein the cyclical selection progresses based on N1, the hop code h and the offset skip value os;
- and
- a combiner operable to select at least one of the N1 delay line phase output signals based on the combiner address, and to forward the at least one of the N1 delay line phase output signals to a modified clock output.
A clock stretcher circuit, comprising:
- a delay locked loop (DLL), having a delay line with a plurality of stages and phase detectors connected to at least a part of the stages in the plurality of stages, to lock the delay line in response to a phase error signal, and a circuit to calculate the phase error signal as a difference between a target active length N1 of the delay line and an actual length EOC;
- a voltage detector which generates a first control signal (hop count) in response to a sensed supply voltage;
- a register to store an offset skip value os;
- a control circuit connected to the phase detectors;
- and
- a clock combiner circuit, having inputs connected to outputs of the plurality of stages of the DLL and to the control circuit, to generate spaced out output clock pulses in dependence on the first control signal, and the offset skip value os.
Dependencies are inferred from the claim text.