Width and frequency conversion with PHY layer devices in PCI-express
AssigneeIntel Corporation
InventorDebendra Das Sharma
Life of this patent
Estimating the term…
Abstract
A system and apparatus can include a first port configured to support a first link width; a second port configured to support a second link width, the second link width different from the first link width; and physical layer logic to receive from the first port a first data block arranged according to the first link width and frequency; create at least one second data block arranged according the second link width and frequency, the at least one second data block including data bytes from the first data block arranged sequentially in the at least one second data block; and transmit the at least one second data block to the second port.
Claims20
An apparatus comprising:
- a first port having a first link width comprising a first number of physical lanes, wherein the first port is receive data at a first frequency from a first integrated circuit block connected to the first port by the first number of physical lanes;
- a second port having a different second link width comprising a different second number of physical lanes, wherein the second port is to transmit data at a different second frequency to a different, second integrated circuitry block connected to the second port by the second number of physical lanes;
- and
- physical layer logic to:
- receive, at the first port, a first data block arranged according to the first link width and the first frequency;
- and
- create at least one second data block arranged according the second link width and the second frequency, wherein the at least one second data block includes information from the first data block arranged sequentially in the at least one second data block.
A method comprising:
- receiving, at physical layer logic of a first port of a converter device, a data block arranged according to a first link width, wherein the first port comprises a first number of physical lanes corresponding to the first link width, and the first port is receive data at a first frequency from a first device;
- mapping, by the physical layer logic, bytes from the data block to a second data block, wherein the second data block is arranged according to a second link width, and the second link width is different from the first link width;
- and
- transmitting the second data block across a link to another second device using a second port of the converter device, wherein the link support comprises a different second number of physical lanes corresponding to the second link width, and the second port transmits data at a second frequency different from the first frequency.
Dependencies are inferred from the claim text.