Level down shifter

A method for level down shifting comprising:

• generating a digital shifted signal and a complementary shifted signal by downshifting voltages of a digital input signal and a complementary input signal using a circuit, wherein the digital input signal and the complementary input signal are in a first voltage domain, the digital shifted signal and the complementary shifted signal are in a second voltage domain, and the second voltage domain has a smaller voltage range than the first voltage domain;
• alternately pulling the digital shifted signal and the complementary shifted signal to an intermediate voltage in response to the digital input signal and the complementary input signal, wherein the intermediate voltage is in the second voltage domain;
• and
• biasing the intermediate voltage from a voltage source of the second voltage domain.

A non-transitory computer readable storage medium storing a library cell defining a level down shifter circuit, the level down shifter circuit comprising:

• a digital input node;
• a complementary input node;
• a digital output node;
• an intermediate node;
• a latch coupled to the digital input node, the complementary input node, and the digital output node, the latch being configured to generate a digital shifted signal on the digital output node and a complementary shifted signal on a complementary shifted node by a voltage downshift of a digital input signal on the digital input node and a complementary input signal on the complementary input node, wherein the digital input signal and the complementary input signal are in a first voltage domain, the digital shifted signal and the complementary shifted signal are in a second voltage domain, and the second voltage domain has a smaller voltage range than the first voltage domain;
• an assist circuit coupled to the digital input node, the complementary input node, the digital output node, and the complementary shifted node, the assist circuit being configured to alternately pull the digital shifted signal and the complementary shifted signal to an intermediate voltage on the intermediate node in response to the digital input signal and the complementary input signal, wherein the intermediate voltage is in the second voltage domain;
• and
• a header configured to bias the intermediate voltage from a second voltage source of the second voltage domain.