Low-skew complementary signal generator
AssigneeMacronix International Co., Ltd.
InventorsShang-Chi Yang, Jhen-Sheng Chih
Life of this patent
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Abstract
A circuit to generate complementary signals comprises a first string of inverters with two inverters in series to produce a true signal in response to an input signal, and a second string of inverters with three inverters in series to produce a complement signal in response to the input signal. A compensation capacitance circuit is connected to a node in the first string of inverters. The compensation capacitance circuit can add capacitance to the node to increase a resistance-capacitance RC delay at the node in a manner which emulates the delay across PVT conditions an inverter in the second string of inverters.
Claims21
A circuit to generate complementary signals, comprising:
- a first string of inverters with an even number of inverters in series to produce a true signal in response to an input signal, and a second string of inverters with an odd number of inverters in series to produce a complement signal in response to the input signal;
- one of the first and second strings having a smaller number of inverters;
- and
- a compensation capacitance circuit connected to a node in the one of the first and second strings having the smaller number of inverters;
- wherein the compensation capacitance circuit includes a first component emulating overlap capacitance of an output node of one of the inverters, and a second component emulating input load capacitance at an input node of one of the inverters.
A circuit to generate complementary signals, comprising:
- a first string of inverters with an even number of inverters in series to produce a true signal in response to an input signal, and a second string of inverters with an odd number of inverters in series to produce a complement signal in response to the input signal;
- one of the first and second strings having a smaller number of inverters;
- and
- a compensation capacitance circuit connected to a node in the one of the first and second strings having the smaller number of inverters, wherein at least one of the inverters in the inverters in the first and second strings includes a PMOS transistor in series with an NMOS transistor having gates connected together, and the compensation capacitance circuit includes:
- a PMOS transistor having a gate connected to its source terminal, and a drain terminal connected to the node, and an NMOS transistor having a gate connected to its source terminal and a drain terminal connected to the node;
- and
- an inverter having an input connected to the node.
An integrated circuit, comprising:
- a macrocell comprising six standard inverter cells having two transistors each and four transistors, one of the standard inverter cells and two of the four transistors being configured as a compensation capacitance circuit, and five of the six standard inverter cells being arranged in a circuit to generate complementary signals.
A circuit to generate complementary signals, comprising:
- a first string of inverters with an even number of inverters in series to produce a true signal in response to an input signal, and a second string of inverters with an odd number of inverters in series to produce a complement signal in response to the input signal;
- one of the first and second strings having a smaller number of inverters;
- and
- means for adding capacitance to a node in said one of the first and second strings having a smaller number of inverters, to emulate overlap capacitance of an output node of one of the inverters, and to emulate input load capacitance at an input node of one of the inverters, to increase a resistance-capacitance RC delay at the node in a manner which emulates the delay across PVT conditions in an inverter in the other string of inverters.
A circuit to generate complementary signals, comprising:
- a first string of inverters with an even number of inverters in series to produce a true signal in response to an input signal, and a second string of inverters with an odd number of inverters in series to produce a complement signal in response to the input signal;
- one of the first and second strings having a smaller number of inverters;
- and
- a compensation capacitance circuit connected to a node in the one of the first and second strings having the smaller number of inverters;
- wherein at least one of the inverters in the inverters in the first and second strings includes a PMOS transistor in series with an NMOS transistor having gates connected together, and the compensation capacitance circuit includes a PMOS transistor having a gate connected to its source terminal, in series with an NMOS transistor having a gate connected to its source terminal.
Dependencies are inferred from the claim text.