Master-slave D flip-flop
AssigneeInfineon Technologies AG
InventorsThomas Kuenemund, Anton Huber
Life of this patent
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Abstract
A master-slave D flip-flop is disclosed having gates configured to supply two second intermediate signals as a function of first intermediate signals and a clock signal, and a slave circuit connected to a transfer circuit to form at least one output signal of the flip-flop from the second intermediate signals. The slave circuit is configured, when the second intermediate signals have, after a preceding pair of states, a predetermined pair of states, to maintain the at least one output signal as given by the preceding pair of states. The transfer circuit has a control input and is configured to generate the second intermediate signals to have the predetermined pair of states in response to a predetermined control signal state at the control input.
Claims16
A master-slave D flip-flop, comprising:
- a master circuit configured to receive an input signal and to produce two first intermediate signals as a function of the input signal;
- a transfer circuit connected to the master circuit and comprising at least two logic gates and a clock connection for applying a clock signal to a respective input of each of the at least two logic gates, each one of the at least two logic gates being configured to supply two second intermediate signals as a function of the first intermediate signals and the clock signal;
- and
- a slave circuit connected to the transfer circuit to form at least one output signal of the master-slave D flip-flop from the two second intermediate signals,
- wherein the slave circuit is configured to, when the two second intermediate signals have a predetermined pair of states after a respective preceding pair of states, maintain the at least one output signal in accordance with the preceding pair of states, and
- wherein the transfer circuit has a control input and is configured to generate the two second intermediate signals having the predetermined pair of states in response to a predetermined control signal state at the control input.
An integrated circuit, comprising:
- a plurality of registers, each register comprising a plurality of flip-flops comprising:
- a master circuit configured to receive an input signal and to produce two first intermediate signals as a function of the input signal;
- a transfer circuit connected to the master circuit and comprising at least two logic gates and a clock connection for applying a clock signal to a respective input of each of the at least two logic gates, each one of the at least two logic gates being configured to supply two second intermediate signals as a function of the first intermediate signals and the clock signal;
- and
- a slave circuit connected to the transfer circuit to form at least one output signal of a respective one of the plurality of flip-flops from the two second intermediate signals,
- wherein the slave circuit is configured to, when the two second intermediate signals have a predetermined pair of states after a respective preceding pair of states, maintain the at least one output signal in accordance with the preceding pair of states, and
- wherein the transfer circuit has a control input and is configured to generate the two second intermediate signals having the predetermined pair of states in response to a predetermined control signal state at the control input.
Dependencies are inferred from the claim text.