Offset compensated differential amplifier and calibration circuit providing increased linear range and granularity of offset compensation and related method

An offset compensated differential amplifier system comprising:

• an offset compensated differential amplifier, comprising:
• a positive primary input and a negative primary input;
• a first amplifier stage configured to generate a first output differential voltage on a positive internal node and a negative internal node based on a primary differential voltage on the positive and negative primary inputs;
• a second amplifier stage coupled to the positive internal node and the negative internal node and configured to generate an output voltage based on an intermediate differential voltage on the positive internal node and the negative internal node;
• and
• an offset compensation circuit comprising:
• a first resistor configured to couple to a supply voltage node and to the positive internal node;
• a second resistor configured to couple to the supply voltage node and to the negative internal node;
• and
• a multi-tan h circuit comprising:
• a plurality of constant current sources;
• and
• a plurality of differential pairs, each differential pair comprising:
• a compensation transistor configured to couple to the positive internal node and to a current input of a corresponding one of the plurality of constant current sources, the compensation transistor comprising a compensation control input configured to receive a compensation control voltage;
• and
• a reference transistor configured to couple to the negative internal node and to the current input of the corresponding one of the plurality of constant current sources, the reference transistor comprising a control input configured to receive one of a plurality of different reference voltages;
• wherein:
• the plurality of differential pairs supplies an offset compensation voltage to the positive and negative internal nodes based on the compensation control voltage and the plurality of different reference voltages;
• and
• the intermediate differential voltage is based on the first output differential voltage and the offset compensation voltage;
• and
• a compensation calibration circuit comprising:
• a switch configured to electrically short the positive primary input to the negative primary input in response to an offset compensation calibration mode;
• a successive approximation register (SAR) analog-to-digital converter (ADC) coupled to the second amplifier stage and configured to generate a binary value based on the output voltage in response to the offset compensation calibration mode;
• and
• a digital-to-analog converter (DAC) configured to generate the compensation control voltage based on the binary value.

A method of compensating an offset voltage in a differential amplifier, the method comprising:

• generating, in a successive approximation register (SAR) analog-to-digital converter (ADC), a binary value based on an output voltage of a differential amplifier in an offset compensation calibration mode;
• generating, in a digital-to-analog converter (DAC), a compensation control voltage in a range from a lower reference voltage to a higher reference voltage based on the binary value;
• coupling a first resistor to a supply voltage node and a positive internal node between a first amplifier stage and a second amplifier stage of the differential amplifier;
• coupling a second resistor to the supply voltage node and a negative internal node between the first amplifier stage and the second amplifier stage of the differential amplifier, the positive and negative internal nodes comprising an intermediate differential voltage;
• and
• coupling a plurality of differential pairs to the positive and negative internal nodes, wherein coupling each one of the plurality of differential pairs comprises:
• coupling a reference transistor to the negative internal node and a constant current source;
• receiving, on a control input of the reference transistor, one of a plurality of different reference voltages from the lower reference voltage to the higher reference voltage;
• coupling a compensation transistor to the positive internal node and the constant current source;
• and
• receiving, on a control input of the compensation transistor, the compensation control voltage generated in the DAC;
• and
• providing, by the plurality of differential pairs, an offset compensation voltage to the positive and negative internal nodes based on the output voltage of the differential amplifier in response to the offset compensation calibration mode.