Multi-level circuit, three-phase multi-level circuit, and control method

A three-phase multi-level circuit, comprising:

• a capacitance branch comprising a first capacitor and a second capacitor that are connected in series, wherein a common terminal of the first capacitor and the second capacitor is grounded;
• a first multi-level generation unit and a second multi-level generation unit, wherein the first multi-level generation unit and the second multi-level generation unit each comprise:
• at least two switching transistor branches that are connected in parallel to the capacitance branch, a first negative coupled inductor, and a second negative coupled inductor, wherein each switching transistor branch comprises a first half bridge and a second half bridge, and a common terminal of the first half bridge and the second half bridge of each switching transistor branch is grounded;
• each input terminal of the first negative coupled inductor is connected to a common terminal of two switching transistors in the first half bridge of only one of the switching transistor branches;
• and each input terminal of the second negative coupled inductor is connected to a common terminal of two switching transistors in the second half bridge of only one of the switching transistor branches;
• a first inverter unit and a second inverter unit, wherein the first inverter unit comprises:
• a third half bridge and a fourth half bridge that are separately connected between the first negative coupled inductor and the second negative coupled inductor in the first multi-level generation unit;
• and the second inverter unit comprises:
• a third half bridge and a fourth half bridge that are separately connected between the first negative coupled inductor and the second negative coupled inductor in the second multi-level generation unit;
• and
• a first power inductor, a second power inductor, and a third power inductor, wherein the first power inductor is connected to a common terminal of two switching transistors in the fourth half bridge in the first inverter unit;
• the second power inductor is separately connected to a common terminal of two switching transistors in the third half bridge in the first inverter unit, and a common terminal of the fourth half bridge in the second inverter unit;
• and the third power inductor is connected to a common terminal of the third half bridge in the second inverter unit.