Methods and apparatus for current sensing and current limiting

An apparatus comprising,

• a cascoded circuit having an output terminal, the cascoded circuit comprising a first transistor and a second transistor, the first transistor having a first current terminal coupled to the output terminal, a second current terminal, and a first control terminal, the second transistor having a third current terminal, a fourth current terminal, and a second control terminal;
• a first amplifier coupled to the first control terminal, the first amplifier configured to control a current through the first transistor;
• a third transistor having a fifth current terminal, a sixth current terminal, and a third control terminal, the third control terminal coupled to the second control terminal, the third transistor configured to determine the current;
• a fourth transistor having a seventh current terminal, an eighth current terminal, and a fourth control terminal, the eighth current terminal coupled to the fifth current terminal, the first amplifier configured to receive a voltage indicating a current through the fourth transistor;
• and
• a second amplifier coupled to the second control terminal and to the third control terminal, the second amplifier configured to control a first voltage across the second transistor and a second voltage across the third transistor.

A system comprising:

• a power sourcing equipment (PSE) circuit having an input terminal and an output terminal, the PSE circuit comprising:
• a current limiting circuit coupled between the input terminal and the output terminal, the current limiting circuit comprising:
• a first transistor having a first current terminal, a second current terminal, and a first control terminal, the first current terminal coupled to the output terminal;
• a second transistor having a third current terminal, a fourth current terminal, and a second control terminal, the third current terminal coupled to the second current terminal and the fourth current terminal coupled to a ground terminal;
• a third transistor having a fifth current terminal, a sixth current terminal, and a third control terminal, the third control terminal coupled to the second control terminal;
• a fourth transistor having a seventh current terminal, an eighth current terminal, and a fourth control terminal, the eighth current terminal coupled to the fifth current terminal;
• a fifth transistor having a ninth current terminal, a tenth current terminal, and a fifth control terminal, the fifth control terminal coupled to the fourth control terminal and the ninth current terminal coupled to the seventh current terminal;
• a first amplifier having a first amplifier output and an inverting input, the first amplifier output coupled to the first control terminal and inverting input coupled to the tenth current terminal;
• and
• a second amplifier having a second amplifier output coupled to the second control terminal and to the third control terminal;
• a PSE port coupled to the output terminal;
• and
• a power device circuit coupled to the PSE port.