Embedded BEOL memory device with top electrode pillar

A method of forming an embedded memory device, the method comprising the steps of:

• depositing a first interlayer dielectric (ILD) on a substrate;
• forming at least one first interconnect in the first ILD over a logic region of the substrate, and at least one second interconnect in the first ILD over a memory region of the substrate;
• depositing a capping layer onto the first ILD over the at least one first interconnect and the at least one second interconnect;
• forming a contact that extends through the capping layer;
• forming a memory film stack on the capping layer, the memory film stack comprising a bottom electrode layer disposed on the capping layer, a dielectric layer disposed on the bottom electrode layer, and a top electrode layer disposed on the dielectric layer;
• patterning the memory film stack into at least one memory device comprising a bottom electrode disposed on the capping layer over the at least one second interconnect, a dielectric element disposed on the bottom electrode, and a top electrode disposed on the dielectric element, wherein the at least one memory device has a width W1, and wherein the contact connects the at least one memory device to the at least one second interconnect;
• patterning the top electrode to form a pillar-shaped top electrode having a width W2, wherein W2<W1, and wherein the bottom electrode has a thickness T1 and the pillar-shaped top electrode has a thickness T2, wherein T2>T1;
• depositing a conformal encapsulation layer over the capping layer and the at least one memory device;
• depositing a second ILD over the conformal encapsulation layer;
• and
• forming at least one first metal line in the second ILD in contact with the at least one first interconnect, and at least one second metal line in the second ILD in contact with the pillar-shaped top electrode.