Method for manufacturing a pressure sensitive field effect transistor including a membrane structure

A method for manufacturing a pressure sensitive transistor, the method comprising:

• forming a channel region between a first contact region and a second contact region in a semiconductor substrate;
• forming a first isolation layer on a main surface of the semiconductor substrate;
• forming a sacrificial structure on the first isolation layer and above the channel region;
• forming a semiconductor layer on the sacrificial structure and on the first isolation layer, wherein the semiconductor layer covers the sacrificial structure;
• forming a further isolation layer on the sacrificial structure;
• removing the sacrificial structure without removing the first isolation layer and without removing the further isolation layer, for providing a cavity between the substrate and the semiconductor layer wherein the semiconductor layer forms a membrane structure having a displaceable center region and forms a control electrode of the pressure sensitive transistor;
• forming a second isolation layer on the membrane structure;
• and
• forming contacting structures for the first contact region, the second contact region and the membrane structure of the pressure sensitive transistor,
• wherein the further isolation layer defines a planar upper boundary of the cavity.

A method for manufacturing a pressure sensitive transistor, the method comprising:

• forming a channel region between a first contact region and a second contact region in a semiconductor substrate;
• forming a first isolation layer on a main surface of the semiconductor substrate;
• forming a sacrificial structure on the first isolation layer and above the channel region;
• forming a semiconductor layer on the sacrificial structure and on the first isolation layer, wherein the semiconductor layer covers the sacrificial structure;
• forming a further isolation layer on the sacrificial structure;
• removing the sacrificial structure without removing the first isolation layer and without removing the further isolation layer, for providing a cavity between the substrate and the semiconductor layer wherein the semiconductor layer forms a membrane structure having a displaceable center region and forms a control electrode of the pressure sensitive transistor;
• forming a second isolation layer on the membrane structure;
• and
• forming contacting structures for the first contact region, the second contact region and the membrane structure of the pressure sensitive transistor,
• wherein a width of the first isolation layer is greater than a width of the cavity, and a width of the further isolation layer is the same as the width of the cavity.